HD74LS77FPEL

更新时间： 2024-09-16 05:35:15

品牌	Logo	应用领域
瑞萨 - RENESAS		锁存器
页数	文件大小	规格书
5页	70K
描述
4-bit Bistable Latches

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中文翻译

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数据手册

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HD74LS77FPEL 数据手册

HD74LS77

4-bit Bistable Latches

REJ03D0418–0300

Rev.3.00

Jul.22.2005

The HD74LS77 is ideally suited for use as temporary storage for binary information between processing units and

input / output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable

(G) is high and the Q output will follow the data input as long as the enable remains high. When the enable goes low,

the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the

enable is permitted to go high.

Features

•

Ordering Information

Package Code

(Previous Code)

Package

Abbreviation

Taping Abbreviation

(Quantity)

Part Name

Package Type

PRSP0014DF-B

(FP-14DAV)

HD74LS77FPEL

SOP-14 pin (JEITA)

EL (2,000 pcs/reel)

Pin Arrangement

Enable 3-4

V_CC

Enable 1-2

GND

(Top view)

Function Table

Inputs

Outputs

Q₀

H; high level, L; low level, X; irrelevant

Rev.3.00, Jul.22.2005, page 1 of 4

12 3 4 5

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与HD74LS77FPEL相关器件

型号	品牌	获取价格	描述	数据表
HD74LS77FP-EL	RENESAS	获取价格	LS SERIES, D LATCH, PDSO14, FP-14DA
HD74LS77FPEL-E	RENESAS	获取价格	IC,LATCH,SINGLE,4-BIT,LS-TTL,SOP,14PIN,PLASTIC
HD74LS77P	ETC	获取价格	4-Bit D-Type Latch
HD74LS77RP	HITACHI	获取价格	D Latch, LS Series, 2-Func, High Level Triggered, 2-Bit, True Output, TTL, PDSO14, FP-14DN
HD74LS77RP-EL	RENESAS	获取价格	LS SERIES, D LATCH, PDSO14, FP-14DN
HD74LS77RP-EL	HITACHI	获取价格	D Latch, LS Series, 2-Func, High Level Triggered, 2-Bit, True Output, TTL, PDSO14, FP-14DN
HD74LS78	HITACHI	获取价格	Dual J-K Flip-Flops(with Preset, Common Clear, and Common Clock)
HD74LS78A	HITACHI	获取价格	Dual J-K Flip-Flops(with Preset, Common Clear, and Common Clock)
HD74LS78A	RENESAS	获取价格	Dual J-K Flip-Flops (with Preset, Common Clear, and Common Clock)
HD74LS78AFP	ETC	获取价格	FLIP-FLOP\|DUAL\|J/K TYPE\|LS-TTL\|SOP\|14PIN\|PLASTIC