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HD74HCT137RPEL PDF预览

HD74HCT137RPEL

更新时间: 2024-09-15 05:35:15
品牌 Logo 应用领域
瑞萨 - RENESAS 解码器解复用器
页数 文件大小 规格书
8页 192K
描述
3-to-8-line Decoder/Demultiplexer with Address Latch

HD74HCT137RPEL 数据手册

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HD74HCT137  
3-to-8-line Decoder/Demultiplexer with Address Latch  
REJ03D0658–0200  
(Previous ADE-205-546)  
Rev.2.00  
Mar 30, 2006  
Description  
The HD74HCT137 implements a three-to-eight line decoder with latches on the three address inputs. When GL goes  
from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GL remains  
high no address changes will be recognized. Output enable controls, G1 and G2, control the state of the outputs  
independently of the select or latch-enable inputs.  
All of the outputs are high unless G1 is high and G2 is low. The HD74HCT137 is ideally suited for the implementation  
of glitch free decoders in stored-address applications in bus oriented systems.  
Features  
High Speed Operation: tpd (A, B, C to Y) = 16.5 ns typ (CL = 50 p
High Output Current: Fanout of 10 LSTTL Loads  
Wide Operating Voltage: VCC = 2 V to 6 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 4 µA
Ordering Information  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
SOP-16 pin (JE
SOP-16 p
HD74HCT137FPEL  
HD74HCT137RPEL  
FP  
RP  
EL (2,000 pcs/reel)  
EL (2,500 pcs/reel)  
A  
Note: Please consult the saage availability.  
Rev.2.00 Mar 30, 2006 page 1 of 7  

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