Datasheet > 逻辑 > 解码器/驱动器> HD74HCT137RP-EL

HD74HCT137RP-EL

更新时间： 2024-09-15 12:58:47

品牌	Logo	应用领域
日立 - HITACHI		解码器解复用器
页数	文件大小	规格书
8页	58K
描述
Decoder/Driver, HCT Series, Inverted Output, CMOS, PDSO16, SOP-16

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HD74HCT137RP-EL 数据手册

HD74HCT137

3-to-8-line Decoder/Demultiplexer with Address Latch

Description

The HD74HCT137 implements a three-to-eight line decoder with latches on the three address inputs.

When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the

latches. As long as GL remains high no address changes will be recognized. Output enable controls, G₁

and G₂, control the state of the outputs independently of the select or latch-enable inputs.

All of the outputs are high unless G₁is high and G₂is low. The HD74HCT137 is ideally suited for the

implementation of glitchfree decoders in stored-address applications in bus oriented systems.

Features

•

LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility

High Speed Operation: t_pd(A, B, C to Y) = 18 ns typ (C_L= 50 pF)

High Output Current: Fanout of 10 LSTTL Loads

Wide Operating Voltage: V_CC= 4.5 to 5.5 V

Low Input Current: 1 µA max

Low Quiescent Supply Current: I_CC(static) = 4 µA max (Ta = 25°C)

12 3 4 5 6 7 8

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型号	品牌	获取价格	描述	数据表
HD74HCT138	RENESAS	获取价格	3-to-8-line Decoder/Demultiplexer
HD74HCT138	HITACHI	获取价格	3-to-8-line Decoder/Demultiplexer
HD74HCT138FP	ETC	获取价格	DECODER/DEMUX\|3-TO-8-LINE\|HCT-CMOS\|SOP\|16PIN\|PLASTIC
HD74HCT138FPEL	RENESAS	获取价格	3-to-8-line Decoder/Demultiplexer
HD74HCT138FP-EL	RENESAS	获取价格	暂无描述
HD74HCT138P	RENESAS	获取价格	3-to-8-line Decoder/Demultiplexer
HD74HCT138P-E	RENESAS	获取价格	HCT SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDIP16, 19.20 X 6.30 MM, 2.54 MM PITCH,
HD74HCT138RP	ETC	获取价格	DECODER/DEMUX\|3-TO-8-LINE\|HCT-CMOS\|SOP\|16PIN\|PLASTIC
HD74HCT138RP-EL	HITACHI	获取价格	暂无描述
HD74HCT138T	ETC	获取价格	DECODER/DEMUX\|3-TO-8-LINE\|HCT-CMOS\|TSSOP\|16PIN\|PLASTIC