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HCTS646MS

更新时间： 2024-11-02 22:49:35
品牌 Logo 应用领域
英特矽尔 - INTERSIL 总线收发器
页数 文件大小 规格书
11页 151K
描述
Radiation Hardened Octal Bus Transceiver/Register, Three-State

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HCTS646MS 数据手册

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HCTS646MS  
Radiation Hardened  
Octal Bus Transceiver/Register, Three-State  
August 1995  
Features  
Pinouts  
24 LEAD CERAMIC DUAL-IN-LINE  
METAL SEAL PACKAGE (SBDIP)  
MIL-STD-1835 CDIP2-T24  
TOP VIEW  
• 3 Micron Radiation Hardened CMOS SOS  
• Total Dose 200K RAD (Si)  
• SEP Effective LET No Upsets: >100 MEV-cm2/mg  
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/  
Bit-Day (Typ)  
CAB  
SAB  
DIR  
A0  
1
2
3
4
5
6
7
8
9
24  
VCC  
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s  
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse  
• Cosmic Ray Upset Rate 2 x 10-9 Errors/Bit Day  
• Latch-Up Free Under Any Conditions  
• Fanout (Over Temperature Range)  
- Bus Driver Outputs - 15 LSTTL Loads  
• Military Temperature Range: -55oC to +125oC  
• Significant Power Reduction Compared to LSTTL ICs  
• DC Operating Voltage Range: 4.5V to 5.5V  
• LSTTL Input Compatibility  
23 CBA  
22 SBA  
21 OE  
20 B0  
19 B1  
18 B2  
17 B3  
16 B4  
15 B5  
14 B6  
13 B7  
A1  
A2  
A3  
A4  
A5  
A6 10  
A7 11  
- VIL = 0.8V Max  
- VIH = VCC/2  
GND 12  
• Input Current Levels Ii ≤ 5µA at VOL, VOH  
Description  
24 LEAD CERAMIC METAL SEAL  
FLATPACK PACKAGE (FLATPACK)  
MIL-STD-1835 CDFP4-F24  
TOP VIEW  
The Intersil HCTS646MS is a Radiation Hardened Three-  
State Octal Bus Tranceiver/Register with Non-Inverting  
outputs. This device is a bus transceiver with D-type flip-flops  
which act as internal storage registers. Data on the A bus or  
the B bus can be clocked into the registers on a High-to-Low  
transition of either CAB ro CBA clock inputs. Output enable  
(OE) and Direction (DIR) inputs control the transceiver func-  
tions. Data present at the high impedance output can be  
stored in either register or both but only one of the two buses  
can be enabled as outputs at any one time. The select con-  
trols (SAB and SBA) can multiplex stored and transparent  
(real time) data. The direction control determines which data  
bus will receive data when the OE pin is LOW. In the high  
impedance mode (OE high), A data can be stored in one reg-  
ister and B data in the other register. Data at the A or B termi-  
nals can be clocked into the storage flip-flops at any time.  
CAB  
SAB  
DIR  
A0  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
1
VCC  
CBA  
SBA  
OE  
B0  
2
3
4
5
A1  
6
A2  
B1  
7
A3  
B2  
8
A4  
B3  
9
A5  
B4  
10  
11  
12  
A6  
B5  
A7  
B6  
GND  
B7  
The HCTS646MS utilizes advanced CMOS/SOS technology  
to achieve high-speed operation. This device is a member of  
radiation hardened, high-speed, CMOS/SOS Logic Family.  
The HCTS646MS is supplied in a 24 lead Ceramic flatpack  
(K suffix) or a SBDIP Package (D suffix).  
Ordering Information  
PART NUMBER  
HCTS646DMSR  
TEMPERATURE RANGE  
SCREENING LEVEL  
Intersil Class S Equivalent  
Intersil Class S Equivalent  
Sample  
PACKAGE  
o
o
-55 C to +125 C  
24 Lead SBDIP  
o
o
HCTS646KMSR  
-55 C to +125 C  
24 Lead Ceramic Flatpack  
24 Lead SBDIP  
o
HCTS646D/Sample  
HCTS646K/Sample  
HCTS646HMSR  
+25 C  
o
+25 C  
Sample  
24 Lead Ceramic Flatpack  
Die  
o
+25 C  
Die  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
Spec Number 518628  
File Number 3074.1  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999706  
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