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HCTS7266D/SAMPLE

更新时间： 2024-11-02 22:19:47
品牌 Logo 应用领域
英特矽尔 - INTERSIL 栅
页数 文件大小 规格书
8页 137K
描述
Radiation Hardened Quad 2-Input Exclusive NOR Gate

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中文翻译

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HCTS7266D/SAMPLE 数据手册

 浏览型号HCTS7266D/SAMPLE的Datasheet PDF文件第2页浏览型号HCTS7266D/SAMPLE的Datasheet PDF文件第3页浏览型号HCTS7266D/SAMPLE的Datasheet PDF文件第4页浏览型号HCTS7266D/SAMPLE的Datasheet PDF文件第5页浏览型号HCTS7266D/SAMPLE的Datasheet PDF文件第6页浏览型号HCTS7266D/SAMPLE的Datasheet PDF文件第7页 
HCTS7266MS  
Radiation Hardened  
Quad 2-Input Exclusive NOR Gate  
August 1995  
Features  
Pinouts  
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL  
PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T14  
TOP VIEW  
• 3 Micron Radiation Hardened CMOS SOS  
• Total Dose 200K RAD (Si)  
• SEP Effective LET No Upsets: >100 MEV-cm2/mg  
A1  
B1  
1
2
3
4
5
6
7
14 VCC  
13 B4  
12 A4  
11 Y4  
10 Y3  
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day  
(Typ)  
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s  
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse  
• Latch-Up Free Under Any Conditions  
• Military Temperature Range: -55oC to +125oC  
• Significant Power Reduction Compared to LSTTL ICs  
• DC Operating Voltage Range: 4.5V to 5.5V  
Y1  
Y2  
A2  
B2  
9
8
B3  
A3  
GND  
• LSTTL Input Compatibility  
- VIL = 0.8V Max  
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE  
(FLATPACK) MIL-STD-1835 CDFP3-F14  
TOP VIEW  
- VIH = 2.0V Min  
• Input Current Levels Ii ≤ 5µA at VOL, VOH  
A1  
B1  
1
2
3
4
5
6
7
14  
13  
VCC  
B4  
A4  
Y4  
Description  
The Intersil HCTS7266MS is a Radiation Hardened quad 2-Input  
exclusive NOR Gate. A logic level high on either one of the inputs  
(A or B) will force the output (y) low. A high on both inputs, or a low  
on both inputs will force the output to a logic high.  
12  
11  
10  
Y1  
Y2  
A2  
Y3  
B2  
B3  
A3  
9
8
The HCTS7266MS utilizes advanced CMOS/SOS technology to  
achieve high-speed operation. This device is a member of radia-  
tion hardened, high-speed, CMOS/SOS Logic Family with TTL  
input compatibility.  
GND  
The HCTS7266MS is supplied in a 14 lead Ceramic flatpack Functional Diagram  
(K suffix) or a SBDIP Package (D suffix).  
An  
Ordering Information  
Yn  
PART  
NUMBER  
TEMPERATURE SCREENING  
RANGE LEVEL  
PACKAGE  
o
o
HCTS7266DMSR  
-55 C to +125 C Intersil Class  
S Equivalent  
14 Lead  
SBDIP  
Bn  
o
o
HCTS7266KMSR  
-55 C to +125 C Intersil Class  
S Equivalent  
14 Lead  
Ceramic  
Flatpack  
TRUTH TABLE  
INPUTS  
OUTPUTS  
o
HCTS7266D/  
Sample  
+25 C  
Sample  
Sample  
14 Lead  
SBDIP  
A
L
B
L
Y
H
L
o
HCTS7266K/  
Sample  
+25 C  
14 Lead  
Ceramic  
Flatpack  
L
H
L
H
H
L
o
HCTS7266HMSR  
+25 C  
Die  
Die  
H
H
NOTE: L = Logic Level Low, H = Logic level High  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
Spec Number 518627  
File Number 3384.1  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
1
12345678

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HCTS74D INTERSIL

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HCTS74DMSH RENESAS

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