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HCTS75K/SAMPLE PDF预览

HCTS75K/SAMPLE

更新时间: 2024-11-03 14:42:31
品牌 Logo 应用领域
瑞萨 - RENESAS 输出元件逻辑集成电路触发器
页数 文件大小 规格书
8页 250K
描述
HCT SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, CDFP16

HCTS75K/SAMPLE 技术参数

生命周期:Obsolete零件包装代码:DFP
包装说明:DFP,针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.69系列:HCT
JESD-30 代码:R-CDFP-F16逻辑集成电路类型:D LATCH
位数:2功能数量:2
端子数量:16输出极性:COMPLEMENTARY
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DFP
封装形状:RECTANGULAR封装形式:FLATPACK
传播延迟(tpd):27 ns认证状态:Not Qualified
座面最大高度:2.92 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
端子形式:FLAT端子节距:1.27 mm
端子位置:DUAL触发器类型:HIGH LEVEL
宽度:6.73 mmBase Number Matches:1

HCTS75K/SAMPLE 数据手册

 浏览型号HCTS75K/SAMPLE的Datasheet PDF文件第2页浏览型号HCTS75K/SAMPLE的Datasheet PDF文件第3页浏览型号HCTS75K/SAMPLE的Datasheet PDF文件第4页浏览型号HCTS75K/SAMPLE的Datasheet PDF文件第5页浏览型号HCTS75K/SAMPLE的Datasheet PDF文件第6页浏览型号HCTS75K/SAMPLE的Datasheet PDF文件第7页 
TM  
HCTS75MS  
Radiation Hardened  
Dual 2-Bit Bistable Transparent Latch  
September 1995  
Features  
Pinouts  
16 LEAD CERAMIC DUAL-IN-LINE  
METAL SEAL PACKAGE (SBDIP)  
MIL-STD-1835 CDIP2-T16, LEAD FINISH C  
TOP VIEW  
• 3 Micron Radiation Hardened SOS CMOS  
• Total Dose 200K RAD (Si)  
2
• SEP Effective LET No Upsets: >100 MEV-cm /mg  
Q0 1  
D0 1  
D1 1  
E 2  
1
2
3
4
5
6
7
8
16 1 Q0  
15 1 Q1  
14 1 Q1  
13 1 E  
-9  
• Single Event Upset (SEU) Immunity < 2 x 10 Errors/Bit-Day  
(Typ)  
12  
• Dose Rate Survivability: >1 x 10 RAD (Si)/s  
10  
• Dose Rate Upset >10 RAD (Si)/s 20ns Pulse  
VCC  
12  
11  
GND  
Q0  
D0 2  
D1 2  
Q1 2  
2
• Latch-Up Free Under Any Conditions  
10 2 Q0  
2 Q1  
o
o
• Military Temperature Range: -55 C to +125 C  
• Significant Power Reduction Compared to LSTTL ICs  
• DC Operating Voltage Range: 4.5V to 5.5V  
9
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE  
(FLATPACK) MIL-STD-1835 CDFP4-F16, LEAD FINISH C  
TOP VIEW  
• LSTTL Input Compatibility  
- VIL = 0.8V Max  
Q0 1  
D0 1  
D1 1  
E 2  
1
1
1
1
Q0  
Q1  
Q1  
E
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
- VIH = VCC/2 Min  
• Input Current Levels Ii 5µA at VOL, VOH  
VCC  
GND  
Description  
D0 2  
D1 2  
Q1 2  
Q0  
Q0  
Q1  
2
2
2
The Intersil HCTS75MS is a Radiation Hardened dual 2-bit  
bistable transparent latch. Each of the two latches are controlled  
by a separate enable input (E) which are active low. E low latches  
the output state.  
Functional Diagram  
The HCTS75MS utilizes advanced CMOS/SOS technology to  
achieve high-speed operation. This device is a member of radia-  
tion hardened, high-speed, CMOS/SOS Logic Family.  
LATCH 0  
2(6)  
16(10  
1(11  
D0  
D
Q
The HCTS75MS is supplied in a 16 lead Ceramic flatpack  
(K suffix) or a SBDIP Package (D suffix).  
LE  
LE  
13(4)  
E
14(8  
15(9  
Ordering Information  
LE  
D
LE  
Q
PART  
TEMPERATURE SCREENING  
RANGE LEVEL  
3(7)  
D1  
NUMBER  
PACKAGE  
HCTS75DMSR  
HCTS75KMSR  
-55oC to +125oC Intersil Class  
S Equivalent  
16 Lead SBDIP  
LATCH 1  
5
VCC  
GND  
12  
-55oC to +125oC Intersil Class  
S Equivalent  
16 Lead Ceramic  
Flatpack  
TRUTH TABLE  
INPUTS  
OUTPUTS  
HCTS75D/  
Sample  
+25oC  
+25oC  
+25oC  
Sample  
Sample  
Die  
16 Lead SBDIP  
D
E
H
H
L
Q
L
Q
H
L
H
X
HCTS75K/  
Sample  
16 Lead Ceramic  
Flatpack  
H
L
Q0  
Q0  
HCTS75HMSR  
Die  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.  
Spec Number 518625  
FN3189.1  
Copyright © Intersil Americas Inc. 2002. All Rights ReservedF  
470  

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