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HCTS75MS

更新时间: 2024-11-02 22:55:03
品牌 Logo 应用领域
英特矽尔 - INTERSIL 锁存器
页数 文件大小 规格书
9页 140K
描述
Radiation Hardened Dual 2-Bit Bistable Transparent Latch

HCTS75MS 数据手册

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HCTS75MS  
Radiation Hardened  
Dual 2-Bit Bistable Transparent Latch  
September 1995  
Features  
Pinouts  
16 LEAD CERAMIC DUAL-IN-LINE  
METAL SEAL PACKAGE (SBDIP)  
MIL-STD-1835 CDIP2-T16, LEAD FINISH C  
TOP VIEW  
• 3 Micron Radiation Hardened SOS CMOS  
• Total Dose 200K RAD (Si)  
• SEP Effective LET No Upsets: >100 MEV-cm2/mg  
Q0 1  
D0 1  
D1 1  
E 2  
1
2
3
4
5
6
7
8
16 1 Q0  
15 1 Q1  
14 1 Q1  
13 1 E  
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day  
(Typ)  
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s  
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse  
• Latch-Up Free Under Any Conditions  
VCC  
12  
11  
GND  
Q0  
D0 2  
D1 2  
Q1 2  
2
10 2 Q0  
2 Q1  
• Military Temperature Range: -55oC to +125oC  
• Significant Power Reduction Compared to LSTTL ICs  
• DC Operating Voltage Range: 4.5V to 5.5V  
9
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE  
(FLATPACK) MIL-STD-1835 CDFP4-F16, LEAD FINISH C  
TOP VIEW  
• LSTTL Input Compatibility  
- VIL = 0.8V Max  
Q0 1  
D0 1  
D1 1  
E 2  
1
1
1
1
Q0  
Q1  
Q1  
E
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
- VIH = VCC/2 Min  
• Input Current Levels Ii 5µA at VOL, VOH  
VCC  
GND  
Description  
D0 2  
D1 2  
Q1 2  
Q0  
Q0  
Q1  
2
2
2
The Intersil HCTS75MS is a Radiation Hardened dual 2-bit  
bistable transparent latch. Each of the two latches are controlled  
by a separate enable input (E) which are active low. E low latches  
the output state.  
Functional Diagram  
The HCTS75MS utilizes advanced CMOS/SOS technology to  
achieve high-speed operation. This device is a member of radia-  
tion hardened, high-speed, CMOS/SOS Logic Family.  
LATCH 0  
2(6)  
16(10  
1(11  
D0  
D
Q
The HCTS75MS is supplied in a 16 lead Ceramic flatpack  
(K suffix) or a SBDIP Package (D suffix).  
LE  
LE  
13(4)  
E
Ordering Information  
14(8  
15(9  
PART  
NUMBER  
TEMPERATURE SCREENING  
RANGE LEVEL  
LE  
D
LE  
Q
PACKAGE  
3(7)  
D1  
o
o
HCTS75DMSR  
-55 C to +125 C Intersil Class  
S Equivalent  
16 Lead SBDIP  
LATCH 1  
5
VCC  
GND  
o
o
HCTS75KMSR  
-55 C to +125 C Intersil Class  
S Equivalent  
16 Lead Ceramic  
Flatpack  
12  
TRUTH TABLE  
o
HCTS75D/  
Sample  
+25 C  
Sample  
Sample  
Die  
16 Lead SBDIP  
INPUTS  
OUTPUTS  
D
E
H
H
L
Q
L
Q
H
o
HCTS75K/  
Sample  
+25 C  
16 Lead Ceramic  
Flatpack  
L
H
X
H
L
o
HCTS75HMSR  
+25 C  
Die  
Q0  
Q0  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
Spec Number 518625  
File Number 3189.1  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999470  

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