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HCTS86K/SAMPLE PDF预览

HCTS86K/SAMPLE

更新时间: 2024-11-03 21:18:07
品牌 Logo 应用领域
瑞萨 - RENESAS 输入元件逻辑集成电路石英晶振
页数 文件大小 规格书
8页 175K
描述
HCT SERIES, QUAD 2-INPUT XOR GATE, CDFP14, CERAMIC, DFP-14

HCTS86K/SAMPLE 技术参数

生命周期:Obsolete零件包装代码:DFP
包装说明:DFP,针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.69系列:HCT
JESD-30 代码:R-CDFP-F14逻辑集成电路类型:XOR GATE
功能数量:4输入次数:2
端子数量:14封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DFP封装形状:RECTANGULAR
封装形式:FLATPACK传播延迟(tpd):20 ns
认证状态:Not Qualified座面最大高度:2.92 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
宽度:6.285 mmBase Number Matches:1

HCTS86K/SAMPLE 数据手册

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TM  
HCTS86MS  
Radiation Hardened  
Quad 2-Input Exclusive OR Gate  
October 1995  
Features  
Pinouts  
14 LEAD CERAMIC DUAL-IN-LINE  
METAL SEAL PACKAGE (SBDIP)  
MIL-STD-1835 CDIP2-T14, LEAD FINISH C  
TOP VIEW  
• 3 Micron Radiation Hardened SOS CMOS  
• Total Dose 200K RAD (Si)  
• SEP Effective LET No Upsets: >100 MEV-cm2/mg  
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day  
(Typ)  
A1  
B1  
1
2
3
4
5
6
7
14 VCC  
13 B4  
12 A4  
11 Y4  
10 B3  
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s  
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse  
• Latch-Up Free Under Any Conditions  
Y1  
A2  
B2  
Y2  
9
8
A3  
Y3  
• Military Temperature Range: -55oC to +125oC  
• Significant Power Reduction Compared to LSTTL ICs  
• DC Operating Voltage Range: 4.5V to 5.5V  
GND  
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE  
(FLATPACK) MIL-STD-1835 CDFP3-F14, LEAD FINISH C  
TOP VIEW  
• LSTTL Input Compatibility  
- VIL = 0.8V Max  
A1  
B1  
1
2
3
4
5
6
7
14  
13  
VCC  
B4  
A4  
Y4  
- VIH = VCC/2 Min  
• Input Current Levels Ii 5µA at VOL, VOH  
12  
11  
10  
9
Y1  
A2  
Description  
B2  
B3  
A3  
Y3  
Y2  
The Intersil HCTS86MS is a Radiation Hardened Quad 2-Input  
Exclusive OR Gate. A high on any one input exclusively will  
change the output to a High state.  
GND  
8
The HCTS86MS utilizes advanced CMOS/SOS technology to  
achieve high-speed operation. This device is a member of radia-  
tion hardened, high-speed, CMOS/SOS Logic Family.  
Functional Diagram  
An  
The HCTS86MS is supplied in a 14 lead Ceramic flatpack  
(K suffix) or a SBDIP Package (D suffix).  
(1, 4, 9, 12)  
Yn  
(3, 6, 8, 11)  
Bn  
Ordering Information  
(2, 5, 10, 13)  
PART  
NUMBER  
TEMPERATURE SCREENING  
RANGE LEVEL  
PACKAGE  
o
o
TRUTH TABLE  
INPUTS  
HCTS86DMSR -55 C to +125 C Intersil Class  
S Equivalent  
14 Lead SBDIP  
OUTPUTS  
o
o
HCTS86KMSR -55 C to +125 C Intersil Class  
S Equivalent  
14 Lead Ceramic  
Flatpack  
An  
L
Bn  
L
Yn  
L
o
HCTS86D/  
Sample  
+25 C  
Sample  
Sample  
Die  
14 Lead SBDIP  
L
H
L
H
H
L
o
HCTS86K/  
Sample  
+25 C  
14 Lead Ceramic  
Flatpack  
H
H
o
H
HCTS86HMSR  
+25 C  
Die  
NOTE: L = Logic Level Low, H = Logic level High  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.  
Spec Number 518623  
File Number 2249.2  
Copyright © Intersil Americas Inc. 2002. All Rights Reserved  
1

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