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HC55142IB PDF预览

HC55142IB

更新时间： 2024-09-18 22:15:15
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英特矽尔 - INTERSIL /
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35页 382K
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Low Power Universal SLIC Family

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HC55142IB 数据手册

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HC55120, HC55121, HC55130, HC55131, HC55140,  
HC55141, HC55142, HC55143, HC55150, HC55151  
TM  
Data Sheet  
June 2000  
File Number 4659.5  
Low Power Universal SLIC Family  
Features  
The UniSLIC14 is a family of Ultra Low Power SLICs. The  
feature set and common pinouts of the UniSLIC14 family  
positions it as a universal solution for: Plain Old Telephone  
Service (POTS), PBX, Central Office, Loop Carrier, Fiber in the  
Loop, ISDN-TA and NT1+, Pairgain and Wireless Local Loop.  
• Ultra Low Active Power (OHT) < 60mW  
• Single/Dual Battery Operation  
• Automatic Silent Battery Selection  
• Power Management/Shutdown  
• Battery Tracking Anti Clipping  
The UniSLIC14 family achieves its ultra low power operation  
through: Its automatic single and dual battery selection  
(based on line length) and battery tracking anti clipping to  
ensure the maximum loop coverage on the lowest battery  
voltage. This architecture is ideal for power critical  
applications such as ISDN NT1+, Pairgain and Wireless  
local loop products.  
• Single 5V Supply with 3V Compatible Logic  
• Zero Crossing Ring Control  
- Zero Voltage On/Zero Current Off  
• Tip/Ring Disconnect  
• Pulse Metering Capability  
• 4 Wire Loopback  
• Programmable Current Feed  
• Programmable Resistive Feed  
• Programmable Loop Detect Threshold  
• Programmable On-Hook and Off-Hook Overheads  
• Programmable Overhead for Pulse Metering  
• Programmable Polarity Reversal Time  
• Selectable Transmit Gain 0dB/-6dB  
• 2 Wire Impedance Set by Single Network  
• Loop and Ground Key Detectors  
• On-Hook Transmission  
The UniSLIC14 family has many user programmable  
features. This family of SLICs delivers a low noise, low  
component count solution for Central Office and Loop  
Carrier universal voice grade designs. The product family  
integrates advanced pulse metering, test and signaling  
capabilities, and zero crossing ring control.  
The UniSLIC14 family is designed in the Intersil “Latch” free  
Bonded Wafer process. This process dielectrically isolates  
the active circuitry to eliminate any leakage paths as found in  
our competition’s JI process. This makes the UniSLIC14  
family compliant with “hot plug” requirements and operation  
in harsh outdoor environments.  
• Common Pinout  
• HC55121  
- Polarity Reversal  
Block Diagram  
• HC55130  
- -63dB Longitudinal Balance  
RRLY  
STATE  
DECODER  
AND  
C1  
RING AND TEST  
RELAY DRIVERS  
C2  
C3  
TRLY1  
TRLY2  
• HC55140  
- Polarity Reversal  
- Ground Start  
- Line Voltage Measurement  
- 2 Wire Loopback  
- -63dB Longitudinal Balance  
DETECTOR  
C4  
C5  
LOGIC  
ZERO CURRENT  
CROSSING  
RING TRIP  
DETECTOR  
DT  
DR  
LOOP CURRENT  
DETECTOR  
SHD  
GKD/LOOP LENGTH  
DETECTOR  
GKD_LVM  
• HC55142  
- Polarity Reversal  
- Ground Start  
CRT_REV_LVM  
POLARITY  
REVERSAL  
ILIM  
- Line Voltage Measurement  
RSYNC_REV  
ROH  
CDC  
RDC_RAC  
RD  
LINE FEED  
CONTROL  
TIP  
- 2.2V  
Pulse Metering  
2-WIRE  
RMS  
- 2 Wire Loopback  
RING  
INTERFACE  
• HC55150  
- Polarity Reversal  
- Line Voltage Measurement  
BGND  
AGND  
V
TX  
4-WIRE INTERFACE  
VF SIGNAL PATH  
V
RX  
- 2.2V  
Pulse Metering  
RMS  
PTG  
- 2 Wire Loopback  
V
BATTERY  
SELECTION  
AND  
BIAS  
NETWORK  
BH  
ZT  
C
H
V
V
BL  
Applications  
PULSE METERING  
SIGNAL PATH  
CC  
• Related Literature  
- AN9871, User’s Guide for UniSLIC14 Eval Board  
SPM  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000  
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