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GVT71256D36T-5

更新时间： 2024-11-07 16:48:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
27页 518K
描述
Cache SRAM, 256KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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GVT71256D36T-5 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
针数：100Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
Factory Lead Time：1 week风险等级：5.91
最长访问时间：3.5 ns最大时钟频率 (fCLK)：200 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：9437184 bit内存集成电路类型：CACHE SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：100
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：256KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：225
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.01 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.51 mA最大供电电压 (Vsup)：3.63 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

GVT71256D36T-5 数据手册

 浏览型号GVT71256D36T-5的Datasheet PDF文件第2页浏览型号GVT71256D36T-5的Datasheet PDF文件第3页浏览型号GVT71256D36T-5的Datasheet PDF文件第4页浏览型号GVT71256D36T-5的Datasheet PDF文件第5页浏览型号GVT71256D36T-5的Datasheet PDF文件第6页浏览型号GVT71256D36T-5的Datasheet PDF文件第7页 
1CY7C1329  
CY7C1360A/GVT71256D36  
CY7C1362A/GVT71512D18  
PRELIMINARY  
256K x 36/512K x 18 Pipelined SRAM  
and a 2-bit counter for internal burst operation. All synchro-  
nous inputs are gated by registers controlled by a posi-  
tive-edge-triggered Clock Input (CLK). The synchronous in-  
puts include all addresses, all data inputs, address-pipelining  
Chip Enable (CE), depth-expansion Chip Enables (CE2 and  
CE2), burst control inputs (ADSC, ADSP, and ADV), Write En-  
ables (BWa, BWb, BWc, BWd, and BWE), and global write  
(GW). However, the CE2 chip enable input is only available for  
the TA package version.  
Features  
• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns  
• Fast clock speed: 225, 200, 166, and 150 MHz  
• Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns  
• Optimal for depth expansion (one cycle chip deselect  
to eliminate bus contention)  
• 3.3V –5% and +10% power supply  
• 3.3V or 2.5V I/O supply  
• 5V tolerant inputs except I/Os  
• Clamp diodes to VSS at all inputs and outputs  
• Common data inputs and data outputs  
• Byte Write Enable and Global Write control  
• Multiple chip enables for depth expansion:  
three chip enables for TA package version and two chip  
enables for B and T package versions  
• Address pipeline capability  
• Address, data, and control registers  
• Internally self-timed Write Cycle  
Asynchronous inputs include the Output Enable (OE) and  
burst mode control (MODE). The data outputs (Q), enabled by  
OE, are also asynchronous.  
Addresses and chip enables are registered with either Ad-  
dress Status Processor (ADSP) or Address Status Controller  
(ADSC) input pins. Subsequent burst addresses can be inter-  
nally generated as controlled by the Burst Advance Pin (ADV).  
Address, data inputs, and write controls are registered on-chip  
to initiate self-timed WRITE cycle. WRITE cycles can be one  
to four bytes wide as controlled by the write control inputs.  
Individual byte write allows individual byte to be written. BWa  
controls DQa. BWb controls DQb. BWc controls DQc. BWd  
controls DQd. BWa, BWb, BWc, and BWd can be active only  
with BWE being LOW. GW being LOW causes all bytes to be  
written. The x18 version only has 18 data inputs/outputs (DQa  
and DQb) along with BWa and BWb (no BWc, BWd, DQc, and  
DQd).  
• Burst control pins (interleaved or linear burst se-  
quence)  
• Automatic power-down for portable applications  
• JTAG boundary scan for B and T package version  
• Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid  
Array) and 100-pin TQFP packages  
For the B and T package versions, four pins are used to imple-  
ment JTAG test capabilities: Test Mode Select (TMS), Test Da-  
ta-In (TDI), Test Clock (TCK), and Test Data-Out (TDO). The  
JTAG circuitry is used to serially shift data to and from the  
device. JTAG inputs use LVTTL/LVCMOS levels to shift data  
during this testing mode of operation. The TA package version  
does not offer the JTAG capability.  
Functional Description  
The Cypress Synchronous Burst SRAM family employs  
high-speed, low-power CMOS designs using advanced tri-  
ple-layer polysilicon, double-layer metal technology. Each  
memory cell consists of four transistors and two high-valued  
resistors.  
The  
CY7C1360A/GVT71256D36  
and  
CY7C1362A/  
The  
CY7C1360A/GVT71256D36  
and  
CY7C1362A/  
GVT71512D18 operate from a +3.3V power supply. All inputs  
and outputs are LVTTL compatible.  
GVT71512D18 SRAMs integrate 262,144x36 and 524,288x18  
SRAM cells with advanced synchronous peripheral circuitry  
Selection Guide  
7C1360A-225  
7C1360A-200  
71256D36-5  
7C1362A-200  
71512D18-5  
7C1360A-166  
71256D36-6  
7C1362A-166  
71512D18-6  
7C1360A-150  
71256D36-6.7  
7C1362A-150  
71512D18-6.7  
71256D36-4.4  
7C1362A-225  
71512D18-4.4  
Maximum Access Time (ns)  
2.5  
570  
10  
3.0  
510  
10  
3.5  
425  
10  
3.5  
380  
10  
Maximum Operating Current (mA)  
Maximum CMOS Standby Current (mA)  
Commercial  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
May 9, 2001  
1234567...27

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与GVT71256D36T-5相关器件

型号 品牌 获取价格 描述 数据表
GVT71256D36TA-6 CYPRESS

获取价格

 		Cache SRAM, 256KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71256D36TA-6.7 CYPRESS

获取价格

 		Cache SRAM, 256KX36, 4.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71256DA18B-5 CYPRESS

获取价格

 		Cache SRAM, 256KX18, 2.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LOW PROFILE, FBGA-1
GVT71256E18B-7 CYPRESS

获取价格

 		Standard SRAM, 256KX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
GVT71256E18B-8 CYPRESS

获取价格

 		Standard SRAM, 256KX18, 8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
GVT71256E18B-9 CYPRESS

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 		Standard SRAM, 256KX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
GVT71256E18T-7 CYPRESS

获取价格

 		Standard SRAM, 256KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-10
GVT71256F18T-3 CYPRESS

获取价格

 		Cache SRAM, 256KX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71256F18T-4 CYPRESS

获取价格

 		Cache SRAM, 256KX18, 3.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71256F18T-6 CYPRESS

获取价格

 		Cache SRAM, 256KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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