Datasheet > GVT71256E18B-9

GVT71256E18B-9

更新时间： 2024-10-30 05:54:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
16页	281K
描述
Standard SRAM, 256KX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119

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GVT71256E18B-9 数据手册

325A

CY7C1325A/GVT71256E18

256K x 18 Synchronous Flow-Through Burst SRAM

The

CY7C1325A/GVT71256E18

SRAM

integrates

Features

262,144x18 SRAM cells with advanced synchronous periph-

eral circuitry and a 2-bit counter for internal burst operation. All

synchronous inputs are gated by registers controlled by a pos-

itive-edge-triggered Clock Input (CLK). The synchronous in-

puts include all addresses, all data inputs, address-pipelining

Chip Enable (CE), depth-expansion Chip Enables (CE2 and

CE2), Burst Control inputs (ADSC, ADSP, and ADV), Write

Enables (WEL, WEH, and BWE), and Global Write (GW).

• Fast access times: 7.5 and 8 ns

• Fast clock speed: 117 and 100 MHz

• Provide high-performance 2-1-1-1 access rate

• Fast OE access times: 4.0 ns

• 3.3V –5% and +10% power supply

• 2.5V or 3.3V I/O supply

• 5V tolerant inputs except I/Os

Asynchronous inputs include the Output Enable (OE) and

Burst Mode Control (MODE), and Sleep Mode Control (ZZ).

The data outputs (DQ), enabled by OE, are also asynchro-

nous.

• Clamp diodes to V_SSQat all inputs and outputs

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

Addresses and chip enables are registered with either Ad-

dress Status Processor (ADSP) or Address Status Controller

(ADSC) input pins. Subsequent burst addresses can be inter-

nally generated as controlled by the Burst Advance pin (ADV).

• Three chip enables for depth expansion and address

pipeline

• Address, data and control registers

• Internally self-timed Write Cycle

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle. Write cycles can be one to

four bytes wide as controlled by the write control inputs. Indi-

vidual byte write allows individual byte to be written. WEL con-

trols DQ1–DQ8 and DQP1. WEH controls DQ9–DQ16 and

DQP2. WEL and WEH can be active only with BWE being

LOW. GW being LOW causes all bytes to be written.

• Burst control pins (interleaved or linear burst se-

quence)

• Automatic power-down for portable applications

• Low profile 119-lead, 14-mm x 22-mm BGA (Ball Grid

Array) and 100-pin TQFP packages

Functional Description

The CY7C1325A/GVT71256E18 operates from a +3.3V pow-

er supply and all outputs operate on a +2.5V supply. All inputs

and outputs are JEDEC standard JESD8-5 compatible. The

device is ideally suited for 486, Pentium®, 680x0, and Power-

PC™ systems and for systems that benefit from a wide syn-

chronous data bus.

The Cypress Synchronous Burst SRAM family employs high-

speed, low-power CMOS designs using advanced triple-layer

polysilicon, double-layer metal technology. Each memory cell

consists of four transistors and two high-valued resistors.

Selection Guide

7C1325A-117

71256E18-7

7C1325A-100

71256E18-8

7C1325A-100

71256E18-9

7C1325A-100

71256E18-10

Maximum Access Time (ns)

7.5

370

Maximum Operating Current (mA)

Maximum CMOS Standby Current (mA)

320

Cypress Semiconductor Corporation

Document #: 38-05118 Rev. *A

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Revised November 12, 2002

12 3 4 5 6 7...16

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与GVT71256E18B-9相关器件

型号	品牌	获取价格	描述	数据表
GVT71256E18T-7	CYPRESS	获取价格	Standard SRAM, 256KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-10
GVT71256F18T-3	CYPRESS	获取价格	Cache SRAM, 256KX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71256F18T-4	CYPRESS	获取价格	Cache SRAM, 256KX18, 3.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71256F18T-6	CYPRESS	获取价格	Cache SRAM, 256KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71256G18B-6	CYPRESS	获取价格	Standard SRAM, 256KX18, 4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
GVT71256G18T-5	CYPRESS	获取价格	Standard SRAM, 256KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71256T18	CYPRESS	获取价格	256K x 18 Synchronous-Pipelined Cache Tag RAM
GVT71256T18T-10	CYPRESS	获取价格	256K x 18 Synchronous-Pipelined Cache Tag RAM
GVT71256T18T-6	CYPRESS	获取价格	256K x 18 Synchronous-Pipelined Cache Tag RAM
GVT71256T18T-67	CYPRESS	获取价格	256K x 18 Synchronous-Pipelined Cache Tag RAM

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