Datasheet > GVT71256ZB36-7.5I

GVT71256ZB36-7.5I

更新时间： 2024-11-25 15:43:59

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟静态存储器内存集成电路
页数	文件大小	规格书
31页	573K
描述
ZBT SRAM, 256KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

GVT71256ZB36-7.5I 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
针数：	100	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.73	最长访问时间：	7.5 ns
其他特性：	FLOW-THROUGH ARCHITECTURE	最大时钟频率 (fCLK)：	100 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PQFP-G100
JESD-609代码：	e0	长度：	20 mm
内存密度：	9437184 bit	内存集成电路类型：	ZBT SRAM
内存宽度：	36	湿度敏感等级：	3
功能数量：	1	端子数量：	100
字数：	262144 words	字数代码：	256000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	256KX36
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装等效代码：	QFP100,.63X.87
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	225
电源：	2.5/3.3,3.3 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大待机电流：	0.03 A
最小待机电流：	3.14 V	子类别：	SRAMs
最大压摆率：	0.35 mA	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	TIN LEAD (800)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	14 mm	Base Number Matches：	1

GVT71256ZB36-7.5I 数据手册

浏览型号GVT71256ZB36-7.5I的Datasheet PDF文件第2页

浏览型号GVT71256ZB36-7.5I的Datasheet PDF文件第3页

浏览型号GVT71256ZB36-7.5I的Datasheet PDF文件第4页

浏览型号GVT71256ZB36-7.5I的Datasheet PDF文件第5页

浏览型号GVT71256ZB36-7.5I的Datasheet PDF文件第6页

浏览型号GVT71256ZB36-7.5I的Datasheet PDF文件第7页

CY7C1357A

CY7C1355A

256K x 36/512K x 18 Synchronous Flow-Thru

SRAM with NoBL™ Architecture

inputs include all addresses, all data inputs, depth-expansion

Chip Enables (CE, CE₂, and CE₃), Cycle Start Input (ADV/LD),

Clock Enable (CEN), Byte Write Enables (BWa, BWb, BWc,

and BWd), and read-write control (WEN). BWc and BWd apply

to CY7C1355A/GVT71256ZB36 only.

Features

• Zero Bus Latency, no dead cycles between write and

read cycles

• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns

• Fast clock speed: 133, 117, and 100 MHz

• Fast OE access time: 6.5, 7.0, 7.5, and 8.0 ns

• Internally synchronized registered outputs eliminate

the need to control OE

Address and control signals are applied to the SRAM during

one clock cycle, and one cycle later, its associated data

occurs, either read or write.

Clock Enable (CEN) pin allows operation of the

CY7C1355A/CY7C1357A/GVT71256ZB36/GVT71512ZB18

to be suspended as long as necessary. All synchronous inputs

are ignored when (CEN) is HIGH and the internal device

registers will hold their previous values.

• 3.3V –5% and +5% power supply

• 3.3V or 2.5V I/O supply

• Single WEN (READ/WRITE) control pin

• Positive clock-edge triggered, address, data, and

control signal registers for fully pipelined applications

• Interleaved or linear four-word burst capability

• Individual byte write (BWa–BWd) control (may be tied

LOW)

• CEN pin to enable clock and suspend operations

• Three chip enables for simple depth expansion

• Automatic Power-down fearture available using ZZ

mode or CE deselect.

There are three Chip Enable pins (CE, CE₂, CE₃) that allow

the user to deselect the device when desired. If any one of

these three are not active when ADV/LD is LOW, no new

memory operation can be initiated and any burst cycle in

progress is stopped. However, any pending data transfers

(read or write) will be completed. The data bus will be in

high-impedance state one cycle after chip is deselected or a

write cycle is initiated.

The

CY7C1355A/GVT71256ZB36

and

CY7C1357A/

GVT71512ZB18 have an on-chip 2-bit burst counter. In the

burst mode, the CY7C1355A/GVT71256ZB36 and

CY7C1357A/GVT71512ZB18 provide four cycles of data for a

single address presented to the SRAM. The order of the burst

sequence is defined by the MODE input pin. The MODE pin

selects between linear and interleaved burst sequence. The

ADV/LD signal is used to load a new external address

(ADV/LD = LOW) or increment the internal burst counter

(ADV/LD = HIGH)

• JTAG boundary scan

• Low-profile 119-bump, 14-mm × 22-mm BGA (Ball Grid

Array) and 100-pin TQFP packages

Functional Description

The

CY7C1355A/GVT71256ZB36

and

CY7C1357A/

GVT71512ZB18 SRAMs are designed to eliminate dead

cycles when transitions from READ to WRITE or vice versa.

These SRAMs are optimized for 100 percent bus utilization

and achieves Zero Bus Latency (ZBL). They integrate 262,144

× 36 and 524,288 × 18 SRAM cells, respectively, with

advanced synchronous peripheral circuitry and a 2-bit counter

for internal burst operation. These employ high-speed, low

power CMOS designs using advanced triple-layer polysilicon,

double-layer metal technology. Each memory cell consists of

Six transistors.

Output Enable (OE), Sleep Enable (ZZ) and burst sequence

select (MODE) are the asynchronous signals. OE can be used

to disable the outputs at any given time. ZZ may be tied to

LOW if it is not used.

Four pins are used to implement JTAG test capabilities. The

JTAG circuitry is used to serially shift data to and from the

device. JTAG inputs use LVTTL/LVCMOS levels to shift data

during this testing mode of operation.

All synchronous inputs are gated by registers controlled by a

positive-edge-triggered Clock Input (CLK). The synchronous

Selection Guide

7C1355A-133

71256ZB36-6.5

7C1357A-133

71512ZB18-6.5

7C1355A-117

71256ZB36-7

7C1357A-117

71512ZB18-7

7C1355A-100

71256ZB36-7.5

7C1357A-100

71512ZB18-7.5

7C1355A1-100

71256ZB36-8

7C1357A1-100

71512ZB18-8

Unit

Maximum Access Time

6.5

410

7.5

350

Maximum Operating Current

Maximum CMOS Standby Current

385

350

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05265 Rev. **

Revised July 11, 2002

12 3 4 5 6 7...31

中文翻译

下载PDF

与GVT71256ZB36-7.5I相关器件

型号	品牌	获取价格	描述	数据表
GVT71256ZB36B-7.5I	CYPRESS	获取价格	ZBT SRAM, 256KX36, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
GVT71256ZB36B-7I	CYPRESS	获取价格	ZBT SRAM, 256KX36, 7ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
GVT71256ZC36	CYPRESS	获取价格	256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
GVT71256ZC36-10	CYPRESS	获取价格	ZBT SRAM, 256KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71256ZC36-10I	CYPRESS	获取价格	256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
GVT71256ZC36-5	CYPRESS	获取价格	ZBT SRAM, 256KX36, 3.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71256ZC36-6	CYPRESS	获取价格	256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
GVT71256ZC36-6I	CYPRESS	获取价格	暂无描述
GVT71256ZC36-7.5I	CYPRESS	获取价格	256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
GVT71256ZC36B-10I	CYPRESS	获取价格	256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture

与GVT71256ZB36-7.5I相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

39
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

31
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

59
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

55

产品中心

服务支持

精选活动

关于我们

帮助中心

GVT71256ZB36-7.5I

GVT71256ZB36-7.5I 技术参数

GVT71256ZB36-7.5I 数据手册

与GVT71256ZB36-7.5I相关器件

与GVT71256ZB36-7.5I相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

GVT71256ZB36-7.5I

GVT71256ZB36-7.5I 技术参数

GVT71256ZB36-7.5I 数据手册

与GVT71256ZB36-7.5I相关器件

与GVT71256ZB36-7.5I相关文章

您还可以找

您在本页遇到什么问题？