Datasheet > GVT71256ZC36B-10I

GVT71256ZC36B-10I

更新时间： 2024-10-30 03:40:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
31页	547K
描述
256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture

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中文翻译

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CY7C1354A/GVT71256ZC36

CY7C1356A/GVT71512ZC18

256K x 36/512K x 18 Pipelined SRAM

with NoBL™ Architecture

inputs include all addresses, all data inputs, depth-expansion

Chip Enables (CE, CE₂, and CE₃), Cycle Start Input (ADV/LD),

Clock Enable (CEN), Byte Write Enables (BWa, BWb, BWc,

and BWd), and Read-Write Control (WEN). BWc and BWd

apply to CY7C1354A/GVT71256ZC36 only.

Features

• Zero Bus Latency, no dead cycles between Write and

Read cycles

• Fast clock speed: 200, 166, 133, 100 MHz

• Fast access time: 3.2, 3.6, 4.2, 5.0 ns

• Internally synchronized registered outputs eliminate

the need to control OE

Address and control signals are applied to the SRAM during

one clock cycle, and two cycles later, its associated data

occurs, either Read or Write.

• Single 3.3V –5% and +5% power supply V_CC

• Separate V_CCQfor 3.3V or 2.5V I/O

• Single WEN (Read/Write) control pin

• Positive clock-edge triggered, address, data, and

control signal registers for fully pipelined applications

clock enable (CEN) pin allows operation of the

CY7C1354A/GVT71256ZC36/CY7C1356A/GVT71512ZC18

to be suspended as long as necessary. All synchronous inputs

are ignored when (CEN) is HIGH and the internal device

registers will hold their previous values.

There are three chip enable pins (CE, CE₂, CE₃) that allow the

user to deselect the device when desired. If any one of these

three are not active when ADV/LD is LOW, no new memory

operation can be initiated and any burst cycle in progress is

stopped. However, any pending data transfers (Read or Write)

will be completed. The data bus will be in high-impedance

state two cycles after chip is deselected or a Write cycle is

initiated.

• Interleaved or linear four-word burst capability

• Individual byte Write (BWa–BWd) control (may be tied

LOW)

• CEN pin to enable clock and suspend operations

• Three chip enables for simple depth expansion

•Automatic power-down feature available using ZZ mode

or CE select

• JTAG boundary scan

• Low-profile 119-bump, 14-mm × 22-mm BGA (Ball Grid

Array), and 100-pin TQFP packages

The

CY7C1354A/GVT71256ZC36

and

CY7C1356A/

GVT71512ZC18 have an on-chip two-bit burst counter. In the

burst mode, the CY7C1354A/GVT71256ZC36 and

CY7C1356A/GVT71512ZC18 provide four cycles of data for a

single address presented to the SRAM. The order of the burst

sequence is defined by the MODE input pin. The MODE pin

selects between linear and interleaved burst sequence. The

ADV/LD signal is used to load a new external address

(ADV/LD = LOW) or increment the internal burst counter

(ADV/LD = HIGH)

Functional Description

The

CY7C1354A/GVT71256ZC36

and

CY7C1356A/

GVT71512ZC18 SRAMs are designed to eliminate dead

cycles when transitioning from Read to Write or vice versa.

These SRAMs are optimized for 100% bus utilization and

achieve Zero Bus Latency

(ZBL )/No Bus Latency

(NoBL ). They integrate 262,144 × 36 and 524,288 × 18

SRAM cells, respectively, with advanced synchronous

peripheral circuitry and a two-bit counter for internal burst

operation. These employ high-speed, low-power CMOS

designs using advanced triple-layer polysilicon, double-layer

metal technology. Each memory cell consists of four

transistors and two high-valued resistors.

Output Enable (OE), Sleep Enable (ZZ) and burst sequence

select (MODE) are the asynchronous signals. OE can be used

to disable the outputs at any given time. ZZ may be tied to

LOW if it is not used.

Four pins are used to implement JTAG test capabilities. The

JTAG circuitry is used to serially shift data to and from the

device. JTAG inputs use LVTTL/LVCMOS levels to shift data

during this testing mode of operation.

All synchronous inputs are gated by registers controlled by a

positive-edge-triggered clock input (CLK). The synchronous

Selection Guide

7C1354A-200

7C1354A-166

71256ZC36-6 71256ZC36-7.5 71256ZC36-10

7C1356A-166 7C1356A-133 7C1356A-100

71512ZC18-6 71512ZC18-7.5 71512ZC18-10 Unit

7C1354A-133

7C1354A-100

71256ZC36-5

7C1356A-200

71512ZC18-5

Maximum Access Time

3.2

560

3.6

480

4.2

410

5.0

350

Maximum Operating Current

Commercial

Maximum CMOS Standby Current Commercial

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05161 Rev. *B

Revised April 25, 2002

12 3 4 5 6 7...31

中文翻译

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与GVT71256ZC36B-10I相关器件

型号	品牌	获取价格	描述	数据表
GVT71256ZC36B-5	CYPRESS	获取价格	ZBT SRAM, 256KX36, 3.2ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
GVT71256ZC36B-6	CYPRESS	获取价格	ZBT SRAM, 256KX36, 3.6ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
GVT71256ZC36B-6I	CYPRESS	获取价格	256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
GVT71256ZC36B-7.5	CYPRESS	获取价格	ZBT SRAM, 256KX36, 4.2ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
GVT71256ZC36B-7.5I	CYPRESS	获取价格	256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
GVT71512B18B-6	CYPRESS	获取价格	Cache SRAM, 512KX18, 6.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
GVT71512B18B-6.5	CYPRESS	获取价格	Standard SRAM, 512KX18, 7ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
GVT71512B18B-7	CYPRESS	获取价格	Standard SRAM, 512KX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
GVT71512B18B-7I	CYPRESS	获取价格	Standard SRAM, 512KX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
GVT71512B18B-8I	CYPRESS	获取价格	Standard SRAM, 512KX18, 9ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119

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