Datasheet > GVT71512B18T-6.5

GVT71512B18T-6.5

更新时间： 2024-10-30 21:13:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟静态存储器内存集成电路
页数	文件大小	规格书
28页	738K
描述
Standard SRAM, 512KX18, 7ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

GVT71512B18T-6.5 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
针数：	100	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.92	Is Samacsys：	N
最长访问时间：	7 ns	其他特性：	FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK)：	133 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
长度：	20 mm	内存密度：	9437184 bit
内存集成电路类型：	STANDARD SRAM	内存宽度：	18
湿度敏感等级：	3	功能数量：	1
端子数量：	100	字数：	524288 words
字数代码：	512000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	512KX18	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP100,.63X.87	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	2.5/3.3,3.3 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大待机电流：	0.01 A	最小待机电流：	3.14 V
子类别：	SRAMs	最大压摆率：	0.36 mA
最大供电电压 (Vsup)：	3.63 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	TIN LEAD	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

GVT71512B18T-6.5 数据手册

1CY7C1361A

CY7C1361A/GVT71256B36

CY7C1363A/GVT71512B18

256K x 36/512K x 18 Synchronous Burst Flowthrough SRAM

and a 2-bit counter for internal burst operation. All synchro-

Features

nous inputs are gated by registers controlled by a positive-

edge-triggered Clock Input (CLK). The synchronous inputs in-

clude all addresses, all data inputs, address-pipelining Chip

Enable (CE), depth-expansion Chip Enables (CE₂and CE₂),

Burst Control Inputs (ADSC, ADSP, and ADV), Write Enables

(BWa, BWb, BWc, BWd, and BWE), and Global Write (GW).

However, the CE₂chip enable input is only available for TA(GV-

TI)/A(CY) package version.

• Fast access times: 6.0, 6.5, 7.0, and 8.0 ns

• Fast clock speed: 150, 133, 117, and 100 MHz

• 1 ns set-up time and hold time

• Fast OE access times: 3.5 ns and 4.0 ns

• 3.3V –5% and +10% power supply

• 3.3V or 2.5V I/O supply

• 5V tolerant inputs except I/Os

Asynchronous inputs include the Output Enable (OE) and

burst mode control (MODE). The data outputs (Q), enabled by

OE, are also asynchronous.

• Clamp diodes to V_SSat all inputs and outputs

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

• Multiple chip enables for depth expansion:

three chip enables for TA(GVTI)/A(CY) package version

and two chip enables for B(GVTI)/BG(CY) and

T(GVTI)/AJ(CY) package versions

• Address pipeline capability

• Address, data and control registers

• Internally self-timed Write Cycle

• Burst control pins (interleaved or linear burst se-

quence)

• Automatic power-down for portable applications

• JTAG boundary scan for B and T package version

• Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid

Array) and 100-pin TQFP packages

Addresses and chip enables are registered with either Ad-

dress Status Processor (ADSP) or Address Status Controller

(ADSC) input pins. Subsequent burst addresses can be inter-

nally generated as controlled by the Burst Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate self-timed WRITE cycle. WRITE cycles can be one

to four bytes wide as controlled by the write control inputs.

Individual byte write allows individual byte to be written. BWa

controls DQa. BWb controls DQb. BWc controls DQc. BWd

controls DQd. BWa, BWb, BWc, and BWd can be active only

with BWE being LOW. GW being LOW causes all bytes to be

written. The x18 version only has 18 data inputs/outputs (DQa

and DQb) along with BWa and BWb (no BWc, BWd, DQc, and

DQd).

For the B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package ver-

sions, four pins are used to implement JTAG test capabilities:

Test Mode Select (TMS), Test Data-In (TDI), Test Clock (TCK),

and Test Data-Out (TDO). The JTAG circuitry is used to serially

shift data to and from the device. JTAG inputs use

LVTTL/LVCMOS levels to shift data during this testing mode of

operation. The TA package version does not offer the JTAG

capability.

Functional Description

The Cypress Synchronous Burst SRAM family employs high-

speed, low-power CMOS designs using advanced triple-layer

polysilicon, double-layer metal technology. Each memory cell

consists of four transistors and two high-valued resistors.

The GVT71256B36/CY7C1361A and GVT71512B18/

CY7C1363A SRAMs integrate 262,144x36 and 524,288x18

SRAM cells with advanced synchronous peripheral circuitry

The GVT71256B36 and GVT71512B18 operate from a +3.3V

power supply. All inputs and outputs are LVTTL compatible.

Selection Guide

7C1361A-150

7C1361A-133

7C1363A-133

71256B36-6.5

71512B18-6.5

7C1361A-117

7C1363A-117

71256B36-7

71512B18-7

7C1361A-100

7C1363A-100

71256B36-8

71512B18-8

7C1363A-150

71256B36-6

71512B18-6

Maximum Access Time (ns)

6.0

400

6.5

360

7.0

320

8.0

270

Maximum Operating Current (mA)

Maximum CMOS Standby Current (mA)

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

June 11, 2001

12 3 4 5 6 7...28

中文翻译

下载PDF

与GVT71512B18T-6.5相关器件

型号	品牌	获取价格	描述	数据表
GVT71512B18T-7	CYPRESS	获取价格	Standard SRAM, 512KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-10
GVT71512B18T-7I	CYPRESS	获取价格	Standard SRAM, 512KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-10
GVT71512B18T-8	CYPRESS	获取价格	Standard SRAM, 512KX18, 9ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71512B18T-8I	CYPRESS	获取价格	Standard SRAM, 512KX18, 9ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71512B18TA-6.5	CYPRESS	获取价格	Standard SRAM, 512KX18, 7ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71512B18TA-7	CYPRESS	获取价格	Standard SRAM, 512KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-10
GVT71512B18TA-7I	CYPRESS	获取价格	Standard SRAM, 512KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-10
GVT71512B18TA-8	CYPRESS	获取价格	Standard SRAM, 512KX18, 9ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71512B18TA-8I	CYPRESS	获取价格	Standard SRAM, 512KX18, 9ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71512B36B-8	ETC	获取价格	x18 Synchronous SRAM

与GVT71512B18T-6.5相关文章

三星深化印度制造布局，供应链本地化进程加速
2024-10-29

16
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

19
纳微科技震撼发布GaNSlim革新氮化镓功率芯片
2024-10-18

43
意法半导体发布第四代SiC技术，助力电动汽车电驱
2024-10-15

50

产品中心

服务支持

精选活动

关于我们

帮助中心

GVT71512B18T-6.5

GVT71512B18T-6.5 技术参数

GVT71512B18T-6.5 数据手册

与GVT71512B18T-6.5相关器件

与GVT71512B18T-6.5相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

GVT71512B18T-6.5

GVT71512B18T-6.5 技术参数

GVT71512B18T-6.5 数据手册

与GVT71512B18T-6.5相关器件

与GVT71512B18T-6.5相关文章

您还可以找

您在本页遇到什么问题？