Datasheet > GVT71512D18B-4.4

GVT71512D18B-4.4

更新时间： 2024-11-21 14:50:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟静态存储器内存集成电路
页数	文件大小	规格书
27页	522K
描述
Cache SRAM, 512KX18, 3ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

GVT71512D18B-4.4 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
针数：	119	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.92	Is Samacsys：	N
最长访问时间：	3 ns	最大时钟频率 (fCLK)：	225 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B119
JESD-609代码：	e0	长度：	22 mm
内存密度：	9437184 bit	内存集成电路类型：	CACHE SRAM
内存宽度：	18	功能数量：	1
端子数量：	119	字数：	524288 words
字数代码：	512000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	512KX18	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA119,7X17,50	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	2.5/3.3,3.3 V
认证状态：	Not Qualified	座面最大高度：	2.4 mm
最大待机电流：	0.01 A	最小待机电流：	3.14 V
子类别：	SRAMs	最大压摆率：	0.57 mA
最大供电电压 (Vsup)：	3.63 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

GVT71512D18B-4.4 数据手册

1CY7C1329

CY7C1360A/GVT71256D36

CY7C1362A/GVT71512D18

PRELIMINARY

256K x 36/512K x 18 Pipelined SRAM

and a 2-bit counter for internal burst operation. All synchro-

nous inputs are gated by registers controlled by a posi-

tive-edge-triggered Clock Input (CLK). The synchronous in-

puts include all addresses, all data inputs, address-pipelining

Chip Enable (CE), depth-expansion Chip Enables (CE₂and

CE₂), burst control inputs (ADSC, ADSP, and ADV), Write En-

ables (BWa, BWb, BWc, BWd, and BWE), and global write

(GW). However, the CE₂chip enable input is only available for

the TA package version.

Features

• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns

• Fast clock speed: 225, 200, 166, and 150 MHz

• Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns

• Optimal for depth expansion (one cycle chip deselect

to eliminate bus contention)

• 3.3V –5% and +10% power supply

• 3.3V or 2.5V I/O supply

• 5V tolerant inputs except I/Os

• Clamp diodes to V_SSat all inputs and outputs

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

• Multiple chip enables for depth expansion:

three chip enables for TA package version and two chip

enables for B and T package versions

• Address pipeline capability

• Address, data, and control registers

• Internally self-timed Write Cycle

Asynchronous inputs include the Output Enable (OE) and

burst mode control (MODE). The data outputs (Q), enabled by

OE, are also asynchronous.

Addresses and chip enables are registered with either Ad-

dress Status Processor (ADSP) or Address Status Controller

(ADSC) input pins. Subsequent burst addresses can be inter-

nally generated as controlled by the Burst Advance Pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate self-timed WRITE cycle. WRITE cycles can be one

to four bytes wide as controlled by the write control inputs.

Individual byte write allows individual byte to be written. BWa

controls DQa. BWb controls DQb. BWc controls DQc. BWd

controls DQd. BWa, BWb, BWc, and BWd can be active only

with BWE being LOW. GW being LOW causes all bytes to be

written. The x18 version only has 18 data inputs/outputs (DQa

and DQb) along with BWa and BWb (no BWc, BWd, DQc, and

DQd).

• Burst control pins (interleaved or linear burst se-

quence)

• Automatic power-down for portable applications

• JTAG boundary scan for B and T package version

• Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid

Array) and 100-pin TQFP packages

For the B and T package versions, four pins are used to imple-

ment JTAG test capabilities: Test Mode Select (TMS), Test Da-

ta-In (TDI), Test Clock (TCK), and Test Data-Out (TDO). The

JTAG circuitry is used to serially shift data to and from the

device. JTAG inputs use LVTTL/LVCMOS levels to shift data

during this testing mode of operation. The TA package version

does not offer the JTAG capability.

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low-power CMOS designs using advanced tri-

ple-layer polysilicon, double-layer metal technology. Each

memory cell consists of four transistors and two high-valued

resistors.

The

CY7C1360A/GVT71256D36

and

CY7C1362A/

The

CY7C1360A/GVT71256D36

and

CY7C1362A/

GVT71512D18 operate from a +3.3V power supply. All inputs

and outputs are LVTTL compatible.

GVT71512D18 SRAMs integrate 262,144x36 and 524,288x18

SRAM cells with advanced synchronous peripheral circuitry

Selection Guide

7C1360A-225

7C1360A-200

71256D36-5

7C1362A-200

71512D18-5

7C1360A-166

71256D36-6

7C1362A-166

71512D18-6

7C1360A-150

71256D36-6.7

7C1362A-150

71512D18-6.7

71256D36-4.4

7C1362A-225

71512D18-4.4

Maximum Access Time (ns)

2.5

570

3.0

510

3.5

425

3.5

380

Maximum Operating Current (mA)

Maximum CMOS Standby Current (mA)

Commercial

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

May 9, 2001

12 3 4 5 6 7...27

中文翻译

下载PDF

与GVT71512D18B-4.4相关器件

型号	品牌	获取价格	描述	数据表
GVT71512D18T-6.7	CYPRESS	获取价格	Cache SRAM, 512KX18, 4.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71512D18TA-6.7	CYPRESS	获取价格	Cache SRAM, 512KX18, 4.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71512DA18B-6	CYPRESS	获取价格	Standard SRAM, 512KX18, 4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
GVT71512DA18T-6	CYPRESS	获取价格	Standard SRAM, 512KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71512DA18TA-5	CYPRESS	获取价格	Standard SRAM, 512KX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-10
GVT71512ZB36-6.5	CYPRESS	获取价格	ZBT SRAM, 512KX18, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-100
GVT71512ZB36-7.5	CYPRESS	获取价格	ZBT SRAM, 512KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-100
GVT71512ZB36-7.5I	CYPRESS	获取价格	ZBT SRAM, 512KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-100
GVT71512ZB36-7I	CYPRESS	获取价格	ZBT SRAM, 512KX18, 7ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-100
GVT71512ZB36B-7.5	CYPRESS	获取价格	ZBT SRAM, 512KX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LBGA-119

与GVT71512D18B-4.4相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

31
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

22
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

51
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

50

产品中心

服务支持

精选活动

关于我们

帮助中心

GVT71512D18B-4.4

GVT71512D18B-4.4 技术参数

GVT71512D18B-4.4 数据手册

与GVT71512D18B-4.4相关器件

与GVT71512D18B-4.4相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

GVT71512D18B-4.4

GVT71512D18B-4.4 技术参数

GVT71512D18B-4.4 数据手册

与GVT71512D18B-4.4相关器件

与GVT71512D18B-4.4相关文章

您还可以找

您在本页遇到什么问题？