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GVT71512DA18B-6 PDF预览

GVT71512DA18B-6

更新时间： 2024-11-21 19:51:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
27页 316K
描述
Standard SRAM, 512KX18, 4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119

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GVT71512DA18B-6 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
针数：119Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.92最长访问时间：4 ns
最大时钟频率 (fCLK)：166 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B119JESD-609代码：e0
长度：22 mm内存密度：9437184 bit
内存集成电路类型：STANDARD SRAM内存宽度：18
功能数量：1端子数量：119
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：512KX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA119,7X17,50
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：2.4 mm最大待机电流：0.01 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.425 mA最大供电电压 (Vsup)：3.63 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

GVT71512DA18B-6 数据手册

 浏览型号GVT71512DA18B-6的Datasheet PDF文件第2页浏览型号GVT71512DA18B-6的Datasheet PDF文件第3页浏览型号GVT71512DA18B-6的Datasheet PDF文件第4页浏览型号GVT71512DA18B-6的Datasheet PDF文件第5页浏览型号GVT71512DA18B-6的Datasheet PDF文件第6页浏览型号GVT71512DA18B-6的Datasheet PDF文件第7页 
CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
256K x 36/512K x 18 Pipelined SRAM  
eral circuitry and a 2-bit counter for internal burst operation. All  
synchronous inputs are gated by registers controlled by a pos-  
itive-edge-triggered Clock Input (CLK). The synchronous in-  
puts include all addresses, all data inputs, address-pipelining  
Features  
• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns  
• Fast clock speed: 225, 200, 166, and 150 MHz  
• Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns  
• Optimal for depth expansion (one cycle chip deselect  
to eliminate bus contention)  
• 3.3V –5% and +10% power supply  
• 3.3V or 2.5V I/O supply  
• 5V tolerant inputs except I/Os  
Chip Enable (CE), depth-expansion Chip Enables (CE and  
2
CE ), burst control inputs (ADSC, ADSP, and ADV), Write En-  
2
ables (BWa, BWb, BWc, BWd, and BWE), and global write  
(GW). However, the CE chip enable input is only available for  
2
TA(GVTI)/A(CY) package version.  
Asynchronous inputs include the Output Enable (OE) and  
burst mode control (MODE). The data outputs (Q), enabled by  
OE, are also asynchronous.  
• Clamp diodes to V at all inputs and outputs  
SS  
• Common data inputs and data outputs  
• Byte Write Enable and Global Write control  
• Multiple chip enables for depth expansion:  
three chip enables for TA(GVTI)/A(CY) package version  
and two chip enables for B(GVTI)/BG(CY) and  
T(GVTI)/AJ(CY) package versions  
• Address pipeline capability  
• Address, data, and control registers  
• Internally self-timed Write Cycle  
• Burst control pins (interleaved or linear burst se-  
quence)  
• Automatic power-down for portable applications  
Addresses and chip enables are registered with either Ad-  
dress Status Processor (ADSP) or Address Status Controller  
(ADSC) input pins. Subsequent burst addresses can be inter-  
nally generated as controlled by the Burst Advance Pin (ADV).  
Address, data inputs, and write controls are registered on-chip  
to initiate self-timed WRITE cycle. WRITE cycles can be one  
to four bytes wide as controlled by the write control inputs.  
Individual byte write allows individual byte to be written. BWa  
controls DQa. BWb controls DQb. BWc controls DQc. BWd  
controls DQd. BWa, BWb, BWc, and BWd can be active only  
with BWE being LOW. GW being LOW causes all bytes to be  
written. The x18 version only has 18 data inputs/outputs (DQa  
and DQb) along with BWa and BWb (no BWc, BWd, DQc, and  
DQd).  
• JTAG boundary scan for B(GVTI)/BG(CY) and  
T(GVTI)/AJ(CY) package version  
For the B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package ver-  
sions, four pins are used to implement JTAG test capabilities:  
Test Mode Select (TMS), Test Data-In (TDI), Test Clock (TCK),  
and Test Data-Out (TDO). The JTAG circuitry is used to serially  
shift data to and from the device. JTAG inputs use  
LVTTL/LVCMOS levels to shift data during this testing mode of  
operation. The TA package version does not offer the JTAG  
capability.  
• Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid  
Array) and 100-pin TQFP packages  
Functional Description  
The Cypress Synchronous Burst SRAM family employs  
high-speed, low power CMOS designs using advanced tri-  
ple-layer polysilicon, double-layer metal technology. Each  
memory cell consists of four transistors and two high valued  
resistors.  
The CY7C1360A1/GVT71256DA36 and CY7C1362A1/  
GVT71512DA18 operate from a +3.3V power supply. All inputs  
and outputs are LVTTL compatible.  
The CY7C1360A1/GVT71256DA36 and CY7C1362A1/  
GVT71512DA18 SRAMs integrate 262,144x36 and  
524,288x18 SRAM cells with advanced synchronous periph-  
Selection Guide  
7C1360A1-225 7C1360A1-200 7C1360A1-166 7C1360A1-150  
71256DA36-4.4 71256DA36-5 71256DA36-6 71256DA36-6.7  
7C1362A1-225 7C1362A1-200 7C1362A1-166 7C1362A1-150  
71512DA18-4.4  
71512DA18-5  
71512DA18-6 71512DA18-6.7  
Maximum Access Time (ns)  
2.5  
570  
10  
3.0  
510  
10  
3.5  
425  
10  
3.5  
380  
10  
Maximum Operating Current (mA)  
Maximum CMOS Standby Current (mA)  
Commercial  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
May 18, 2000  
1234567...27

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与GVT71512DA18B-6相关器件

型号 品牌 获取价格 描述 数据表
GVT71512DA18T-6 CYPRESS

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 		Standard SRAM, 512KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71512DA18TA-5 CYPRESS

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 		Standard SRAM, 512KX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-10
GVT71512ZB36-6.5 CYPRESS

获取价格

 		ZBT SRAM, 512KX18, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-100
GVT71512ZB36-7.5 CYPRESS

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 		ZBT SRAM, 512KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-100
GVT71512ZB36-7.5I CYPRESS

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 		ZBT SRAM, 512KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-100
GVT71512ZB36-7I CYPRESS

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 		ZBT SRAM, 512KX18, 7ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-100
GVT71512ZB36B-7.5 CYPRESS

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 		ZBT SRAM, 512KX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LBGA-119
GVT71512ZB36B-7.5I CYPRESS

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 		ZBT SRAM, 512KX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LBGA-119
GVT71512ZB36B-7I CYPRESS

获取价格

 		ZBT SRAM, 512KX18, 7ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LBGA-119
GVT71512ZC18 CYPRESS

获取价格

 		256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture

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