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GVT71512C18T-5 PDF预览

GVT71512C18T-5

更新时间： 2024-10-30 03:40:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
27页 308K
描述
256K x 36/512K x 18 Pipelined SRAM

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中文翻译

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GVT71512C18T-5 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
针数：100Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.92最长访问时间：3 ns
最大时钟频率 (fCLK)：200 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e0
长度：20 mm内存密度：9437184 bit
内存集成电路类型：CACHE SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：100字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：512KX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.01 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.51 mA
最大供电电压 (Vsup)：3.63 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm

GVT71512C18T-5 数据手册

 浏览型号GVT71512C18T-5的Datasheet PDF文件第2页浏览型号GVT71512C18T-5的Datasheet PDF文件第3页浏览型号GVT71512C18T-5的Datasheet PDF文件第4页浏览型号GVT71512C18T-5的Datasheet PDF文件第5页浏览型号GVT71512C18T-5的Datasheet PDF文件第6页浏览型号GVT71512C18T-5的Datasheet PDF文件第7页 
CY7C1366A/GVT71256C36  
CY7C1367A/GVT71512C18  
256K x 36/512K x 18 Pipelined SRAM  
and a 2-bit counter for internal burst operation. All synchro-  
Features  
nous inputs are gated by registers controlled by  
a
• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns  
• Fast clock speed: 225 MHz, 200 MHz, 166 MHz, and  
150 MHz  
• Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns  
• Optimalforperformance(twocyclechipdeselect,depth  
expansion without wait state)  
• 3.3V –5% and +10% power supply  
• 3.3V or 2.5V I/O supply  
• 5V tolerant inputs except I/Os  
positive-edge-triggered Clock Input (CLK). The synchronous  
inputs include all addresses, all data inputs, address-pipelin-  
ing Chip Enable (CE), depth-expansion Chip Enables (CE  
2
and CE ), Burst Control Inputs (ADSC, ADSP, and ADV), Write  
2
Enables (BWa, BWb, BWc, BWd, and BWE), and Global Write  
(GW). However, the CE Chip Enable input is only available for  
2
the TA(GVTI)/A(CY) package version.  
Asynchronous inputs include the Output Enable (OE) and  
Burst Mode Control (MODE). The data outputs (Q), enabled  
by OE, are also asynchronous.  
• Clamp diodes to V at all inputs and outputs  
SS  
Addresses and chip enables are registered with either Ad-  
dress Status Processor (ADSP) or Address Status Controller  
(ADSC) input pins. Subsequent burst addresses can be inter-  
nally generated as controlled by the Burst Advance Pin (ADV).  
• Common data inputs and data outputs  
• Byte Write Enable and Global Write control  
• Multiple chip enables for depth expansion:  
three chip enables for TA(GVTI)/A(CY) package version  
and two chip enables for B(GVTI)/BG(CY) and  
T(GVTI)/AJ(CY) package versions  
• Address pipeline capability  
• Address, data and control registers  
• Internally self-timed Write Cycle  
• Burst control pins (interleaved or linear burst  
sequence)  
• Automatic power-down for portable applications  
• JTAG boundary scan for B and T package version  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed WRITE cycle. WRITE cycles can be one  
to four bytes wide, as controlled by the write control inputs.  
Individual byte write allows an individual byte to be written.  
BWa controls DQa. BWb controls DQb. BWc controls DQc.  
BWd controls DQd. BWa, BWb, BWc, and BWd can be active  
only with BWE being LOW. GW being LOW causes all bytes  
to be written. The x18 version only has 18 data inputs/outputs  
(DQa and DQb) along with BWa and BWb (no BWc, BWd,  
DQc, and DQd).  
For the B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package ver-  
sions, four pins are used to implement JTAG test capabilities:  
Test Mode Select (TMS), Test Data-In (TDI), Test Clock (TCK),  
and Test Data-Out (TDO). The JTAG circuitry is used to serially  
shift data to and from the device. JTAG inputs use  
LVTTL/LVCMOS levels to shift data during this testing mode of  
operation. The TA package version does not offer the JTAG  
capability.  
• Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid  
Array) and 100-pin TQFP packages  
Functional Description  
The Cypress Synchronous Burst SRAM family employs  
high-speed, low power CMOS designs using advanced  
triple-layer polysilicon, double-layer metal technology. Each  
memory cell consists of four transistors and two high valued  
resistors.  
The  
CY7C1366A/GVT71256C36  
and  
CY7C1367A/  
GVT71512C18 operate from a +3.3V power supply. All inputs  
and outputs are LVTTL compatible.  
The  
CY7C1366A/GVT71256C36  
and  
CY7C1367A/  
GVT71512C18 SRAMs integrate 262,144 x 36 and 524,288 x  
18 SRAM cells with advanced synchronous peripheral circuitry  
Selection Guide  
7C1366A-225/  
7C1366A-200/  
71256C36-5  
7C1367A-200/  
71512C18-5  
7C1366A-166/  
71256C36-6  
7C1367A-166/  
71512C18-6  
7C1366A-150/  
71256C36-6.7  
7C1367A-150/  
71512C18-6.7  
71256C36-4.4  
7C1367A-225/  
71512C18-4.4  
Maximum Access Time (ns)  
2.5  
570  
10  
3.0  
510  
10  
3.5  
425  
10  
3.5  
380  
10  
Maximum Operating Current (mA)  
Maximum CMOS Standby Current (mA)  
Commercial  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
June 12, 2001  
1234567...27

中文翻译

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GVT71512C18T-6.7 CYPRESS

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GVT71512C18TA-4.4 CYPRESS

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GVT71512C18TA-5 CYPRESS

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 		256K x 36/512K x 18 Pipelined SRAM
GVT71512C18TA-5I CYPRESS

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GVT71512C18TA-6 CYPRESS

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 		256K x 36/512K x 18 Pipelined SRAM
GVT71512C18TA-6.7 CYPRESS

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GVT71512C18TA-6.7I CYPRESS

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 		暂无描述
GVT71512D18B-4.4 CYPRESS

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 		Cache SRAM, 512KX18, 3ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
GVT71512D18T-6.7 CYPRESS

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 		Cache SRAM, 512KX18, 4.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71512D18TA-6.7 CYPRESS

获取价格

 		Cache SRAM, 512KX18, 4.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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