Datasheet > GVT71256F18T-6

GVT71256F18T-6

更新时间： 2024-11-25 19:51:43

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟静态存储器内存集成电路
页数	文件大小	规格书
12页	150K
描述
Cache SRAM, 256KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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技术参数
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GVT71256F18T-6 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
针数：	100	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
Factory Lead Time：	1 week	风险等级：	5.92
Is Samacsys：	N	最长访问时间：	4 ns
其他特性：	PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	117 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PQFP-G100
JESD-609代码：	e0	长度：	20 mm
内存密度：	4718592 bit	内存集成电路类型：	CACHE SRAM
内存宽度：	18	湿度敏感等级：	3
功能数量：	1	端子数量：	100
字数：	262144 words	字数代码：	256000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	256KX18
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装等效代码：	QFP100,.63X.87
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	225
电源：	2.5/3.3,3.3 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大待机电流：	0.01 A
最小待机电流：	3.14 V	子类别：	SRAMs
最大压摆率：	0.35 mA	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN LEAD (800)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	14 mm	Base Number Matches：	1

GVT71256F18T-6 数据手册

CY7C1328A/GVT71256F18

CY7C1348A/GVT71128F36

PRELIMINARY

128K x 36/256K x 18

Synchronous-Pipelined Cache RAM

and a 2-bit counter for internal burst operation. All synchro-

nous inputs are gated by registers controlled by a posi-

tive-edge-triggered Clock Input (CLK). The synchronous in-

puts include all addresses, all data inputs, address-pipelining

Chip Enable (CE), depth-expansion Chip Enables (CE2 and

CE2), Burst Control inputs (ADSC, ADSP, and ADV), Write En-

ables (BW1, BW2, BW3, BW4, and BWE), and Global Write

Features

• Fast access times: 3.5, 3.8, and 4.0 ns

• Fast clock speed: 166, 150, 133, and 117 MHz

• Provide high performance 3-1-1-1 access rate

• Fast OE access times: 3.5 ns and 3.8 ns

• Optimal for performance (double cycle chip deselect,

depth expansion without wait state)

• 3.3V –5% and +10% core power supply

• 2.5V or 3.3V I/O supply

• 5V tolerant inputs except I/Os

(GW).

Asynchronous inputs include the Output Enable (OE) and

Burst Mode Control (MODE). The data outputs (Q), enabled

by OE, are also asynchronous.

Addresses and chip enables are registered with either Ad-

dress Status Processor (ADSP) or Address Status Controller

(ADSC) input pins. Subsequent burst addresses can be inter-

nally generated as controlled by the Burst Advance pin (ADV).

• Clamp diodes to V

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

at all inputs and outputs

SSQ

• Three chip enables for depth expansion and address

pipeline

• Address, data and control registers

• Internally self-timed Write Cycle

• Burst control pins (interleaved or linear burst se-

quence)

• Automatic power-down for portable applications

• High-density, high-speed packages

Address, data inputs, and write controls are registered on-chip

to initiate self-timed WRITE cycle. WRITE cycles can be one

to four bytes wide as controlled by the write control inputs.

Individual byte write allows individual byte to be written. BW1

controls DQ1–DQ8 and DQP1. BW2 controls DQ9–DQ16 and

DQP2. BW3 controls DQ17–DQ24 and DQP3. BW4 controls

DQ25–DQ32 and DQP4. BW1, BW2, BW3, and BW4 can be

active only with BWE being LOW. GW being LOW causes all

bytes to be written. WRITE pass-through capability allows writ-

ten data available at the output for the immediately next READ

cycle. This device also incorporates pipelined enable circuit for

easy depth expansion without penalizing system performance.

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low-power CMOS designs using advanced tri-

ple-layer polysilicon, double-layer metal technology. Each

memory cell consists of four transistors and two high-valued

resistors.

The CY7C1348A/GVT71128F36/CY7C1328A/GVT71256F18

operates from a +3.3V core power supply and all outputs op-

erate on a +2.5V supply. All inputs and outputs are JEDEC

standard JESD8-5 compatible. The device is ideally suited for

486, Pentium®, 680x0, and PowerPC™ systems and for sys-

tems that benefit from a wide synchronous data bus.

The

CY7C1348A/GVT71128F36

and

CY7C1328A/

GVT71256F18 SRAM integrate 262,144x18 and 131,072x36

SRAM cells with advanced synchronous peripheral circuitry

Selection Guide

7C1328A-166

7C1328A-150

71256F18-4

7C1348A-150

71128F36-4

7C1328A-133

71256F18-5

7C1348A-133

71128F36-5

7C1328A-117

71256F18-6

7C1348A-117

71128F36-6

71256F18-3

7C1348A-166

71128F36-3

Maximum Access Time (ns)

3.5

425

3.8

400

4.0

375

4.0

350

Maximum Operating Current (mA)

Maximum CMOS Standby Current (mA)

Pentium is a registered trademark of Intel Corporation.

PowerPC is a trademark of IBM Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

June 14, 2000

12 3 4 5 6 7...12

中文翻译

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与GVT71256F18T-6相关器件

型号	品牌	获取价格	描述	数据表
GVT71256G18B-6	CYPRESS	获取价格	Standard SRAM, 256KX18, 4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
GVT71256G18T-5	CYPRESS	获取价格	Standard SRAM, 256KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71256T18	CYPRESS	获取价格	256K x 18 Synchronous-Pipelined Cache Tag RAM
GVT71256T18T-10	CYPRESS	获取价格	256K x 18 Synchronous-Pipelined Cache Tag RAM
GVT71256T18T-6	CYPRESS	获取价格	256K x 18 Synchronous-Pipelined Cache Tag RAM
GVT71256T18T-67	CYPRESS	获取价格	256K x 18 Synchronous-Pipelined Cache Tag RAM
GVT71256T18T-7.5	CYPRESS	获取价格	Cache Tag SRAM, 256KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71256T18T-75	CYPRESS	获取价格	256K x 18 Synchronous-Pipelined Cache Tag RAM
GVT71256ZB36-7.5	CYPRESS	获取价格	ZBT SRAM, 256KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71256ZB36-7.5I	CYPRESS	获取价格	ZBT SRAM, 256KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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