Datasheet > GVT71256T18T-75

GVT71256T18T-75

更新时间： 2024-10-29 10:37:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
24页	234K
描述
256K x 18 Synchronous-Pipelined Cache Tag RAM

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GVT71256T18T-75 数据手册

327

CY7C1359A/GVT71256T18

256K x 18 Synchronous-Pipelined Cache Tag RAM

All synchronous inputs are gated by registers controlled by a

positive-edge-triggered Clock Input (CLK). The synchronous

Features

• Fast match times: 3.5, 3.8, 4.0 and 4.5 ns

• Fast clock speed: 166, 150, 133, and 100 MHz

• Fast OE access times: 3.5, 3.8, 4.0 and 5.0 ns

• Pipelined data comparator

• Data input register load control by DEN

• Optimal for depth expansion (one cycle chip deselect

to eliminate bus contention)

• 3.3V –5% and +10% core power supply

• 2.5V or 3.3V I/O supply

• 5V tolerant inputs except I/Os

• Clamp diodes to V_SSat all inputs and outputs

• Common data inputs and data outputs

• JTAG boundary scan

inputs include all addresses, all data inputs, address-pipelin-

ing Chip Enable (CE), depth-expansion Chip Enables (CE₂

and CE₂), Burst Control Inputs (ADSC, ADSP, and ADV), Write

Enables (WEL, WEH, and BWE), Global Write (GW), and Data

Input Enable (DEN).

Asynchronous inputs include the Burst Mode Control (MODE),

the Output Enable (OE) and the Match Output Enable (MOE).

The data outputs (Q) and Match Output (MATCH), enabled by

OE and MOE respectively, are also asynchronous.

Addresses and chip enables are registered with either Ad-

dress Status Processor (ADSP) or Address status Controller

(ADSC) input pins. Subsequent burst addresses can be inter-

nally generated as controlled by the Burst Advance pin (ADV).

Data inputs are registered with Data Input Enable (DEN) and

chip enable pins (CE, CE₂, and CE₂). The outputs of the data

input registers are compared with data in the memory array

and a match signal is generated. The match output is gated

into a pipeline register and released to the match output pin at

the next rising edge of Clock (CLK).

• Byte Write Enable and Global Write control

• Three chip enables for depth expansion and address

pipeline

• Address, data, and control registers

• Internally self-timed Write Cycle

Address, data inputs, and write controls are registered on-chip

to initiate self-timed WRITE cycle. WRITE cycles can be one

to two bytes wide as controlled by the write control inputs. In-

dividual byte write allows individual byte to be written. WEL

controls DQ1–DQ9. WEH controls DQ10–DQ18. WEL and

WEH can be active only with BWE being LOW. GW being LOW

causes all bytes to be written.

• Burst control pins (interleaved or linear burst se-

quence)

• Automatic power-down for portable applications

• Low-profile JEDEC standard 100-pin TQFP package

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low power CMOS designs using advanced tri-

ple-layer polysilicon, double-layer metal technology. Each

memory cell consists of four transistors and two high valued

resistors.

The CY7C1359C/GVT71256T18 operates from a +3.3V pow-

er supply with output power supply being +2.5V or +3.3V. All

inputs and outputs are LVTTL compatible. The device is ideally

suited for address tag RAM for up to 8 MB secondary cache.

Selection Guide

7C1359A-166

71256T36-6

7C1359A-150

71256T36-6.7

7C1359A-133

71256T36-7.5

7C1359A-100

71256T36-10

Maximum Access Time (ns)

3.5

310

3.8

275

4.0

250

4.5

190

Maximum Operating Current (mA)

Maximum CMOS Standby Current (mA)

Cypress Semiconductor Corporation

Document #: 38-05120 Rev. **

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Revised September 13, 2001

12 3 4 5 6 7...24

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与GVT71256T18T-75相关器件

型号	品牌	获取价格	描述	数据表
GVT71256ZB36-7.5	CYPRESS	获取价格	ZBT SRAM, 256KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71256ZB36-7.5I	CYPRESS	获取价格	ZBT SRAM, 256KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71256ZB36B-7.5I	CYPRESS	获取价格	ZBT SRAM, 256KX36, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
GVT71256ZB36B-7I	CYPRESS	获取价格	ZBT SRAM, 256KX36, 7ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
GVT71256ZC36	CYPRESS	获取价格	256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
GVT71256ZC36-10	CYPRESS	获取价格	ZBT SRAM, 256KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71256ZC36-10I	CYPRESS	获取价格	256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
GVT71256ZC36-5	CYPRESS	获取价格	ZBT SRAM, 256KX36, 3.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71256ZC36-6	CYPRESS	获取价格	256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
GVT71256ZC36-6I	CYPRESS	获取价格	暂无描述

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