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GTL2008PW,118 PDF预览

GTL2008PW,118

更新时间： 2024-11-26 19:43:51
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管接口集成电路锁存器
页数 文件大小 规格书
22页 189K
描述
GTL2008 - 12-bit GTL to LVTTL translator with power good control and high-impedance LVTTL and GTL outputs TSSOP2 28-Pin

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GTL2008PW,118 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：TSSOP2包装说明：TSSOP, TSSOP28,.25
针数：28Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.33
最大延迟：350 ns接口集成电路类型：GTL TO TTL TRANSCEIVER
JESD-30 代码：R-PDSO-G28JESD-609代码：e4
长度：9.7 mm湿度敏感等级：1
位数：12功能数量：1
端子数量：28最高工作温度：85 °C
最低工作温度：-40 °C输出锁存器或寄存器：NONE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP28,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified座面最大高度：1.1 mm
子类别：Other Interface ICs最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：4.4 mm
Base Number Matches：1

GTL2008PW,118 数据手册

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GTL2008  
12-bit GTL to LVTTL translator with power good control and  
high-impedance LVTTL and GTL outputs  
Rev. 04 — 19 February 2010  
Product data sheet  
1. General description  
The GTL2008 is a customized translator between dual Xeon processors, Platform Health  
Management, South Bridge and Power Supply LVTTL and GTL signals.  
Functionally and footprint identical to the GTL2007, the GTL2008 LVTTL and GTL outputs  
were changed to put them into a high-impedance state when EN1 and EN2 are LOW, with  
the exception of 11BO because its normal state is LOW, so it is forced LOW. EN1 and  
EN2 will remain LOW until VCC is at normal voltage, the other inputs are in valid states  
and VREF is at its proper voltage to assure that the outputs will remain high-impedance  
through power-up.  
The GTL2008 has the enable function that disables the error output to the monitoring  
agent for platforms that monitor the individual error conditions from each processor. This  
enable function can be used so that false error conditions are not passed to the  
monitoring agent when the system is unexpectedly powered down. This unexpected  
power-down could be from a power supply overload, a CPU thermal trip, or some other  
event of which the monitoring agent is unaware.  
A typical implementation would be to connect each enable line to the system power good  
signal or the individual enables to the VRD power good for each processor.  
Typically Xeon processors specify a VTT of 1.1 V to 1.2 V, as well as a nominal Vref of  
0.73 V to 0.76 V. To allow for future voltage level changes that may extend Vref to 0.63 of  
V
TT (minimum of 0.693 V with VTT of 1.1 V) the GTL2008 allows a minimum Vref of 0.66 V.  
Characterization results show that there is little DC or AC performance variation between  
these Vref levels.  
2. Features and benefits  
„ Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver  
„ Operates at GTL−/GTL/GTL+ signal levels  
„ EN1 and EN2 disable error output  
„ All LVTTL and GTL outputs are put in a high-impedance state when EN1 and EN2 are  
LOW  
„ 3.0 V to 3.6 V operation  
„ LVTTL I/O not 5 V tolerant  
„ Series termination on the LVTTL outputs of 30 Ω  
„ ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per  
JESD22-A115, and 1000 V CDM per JESD22-C101  
 
 
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