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GTL2012DP PDF预览

GTL2012DP

更新时间: 2024-11-28 07:02:15
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
14页 91K
描述
2-bit LVTTL to GTL transceiver

GTL2012DP 数据手册

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GTL2012  
2-bit LVTTL to GTL transceiver  
Rev. 01 — 9 August 2007  
Product data sheet  
1. General description  
The GTL2012 is a 2-bit translating transceiver designed for 3.3 V system interface with a  
GTL/GTL/GTL+ bus.  
The direction pin (DIR) allows the part to function as either a GTL-to-LVTTL sampling  
receiver or as an LVTTL-to-GTL interface.  
The GTL2012 LVTTL inputs (only) are tolerant up to 5.5 V allowing direct access to TTL or  
5 V CMOS inputs.  
2. Features  
I Operates as a 2-bit GTL/GTL/GTL+ sampling receiver or as an LVTTL to  
GTL/GTL/GTL+ driver  
I 3.0 V to 3.6 V operation with 5 V tolerant LVTTL input  
I GTL input and output 3.6 V tolerant  
I Vref adjustable from 0.5 V to 0.5VCC  
I Partial power-down permitted  
I Latch-up protection exceeds 500 mA per JESD78  
I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per  
JESD22-A115, and 1000 V CDM per JESD22-CC101  
I Package offered: TSSOP8 (MSOP8) and VSSOP8  
3. Quick reference data  
Table 1.  
Quick reference data  
Recommended operating conditions; Tamb = 25 °C  
Symbol  
Ci  
Parameter  
Conditions  
Min  
Typ[1] Max Unit  
input capacitance  
input/output capacitance  
control inputs; VI = 3.0 V or 0 V  
A port; VO = 3.0 V or 0 V  
B port; VO = VTT or 0 V  
-
-
-
2
2.5  
6
pF  
pF  
pF  
Cio  
4.6  
3.4  
4.3  
GTL; Vref = 0.8 V; VTT = 1.2 V  
tPLH  
tPHL  
tPLH  
tPHL  
LOW-to-HIGH propagation delay  
An to Bn; see Figure 4  
An to Bn; see Figure 4  
Bn to An; see Figure 5  
Bn to An; see Figure 5  
-
-
-
-
2.8  
3.4  
5.2  
4.9  
5
7
8
7
ns  
ns  
ns  
ns  
HIGH-to-LOW propagation delay  
LOW-to-HIGH propagation delay  
HIGH-to-LOW propagation delay  
[1] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.  

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