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GTL2018PW

更新时间： 2024-11-26 07:02:15

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
14页	87K
描述
8-bit LVTTL to GTL transceiver

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GTL2018PW 数据手册

GTL2018

8-bit LVTTL to GTL transceiver

Rev. 01 — 15 February 2007

Product data sheet

1. General description

The GTL2018 is an octal translating transceiver designed for 3.3 V LVTTL system

interface with a GTL−/GTL/GTL+ bus.

The direction pin (DIR) allows the part to function as either a GTL-to-LVTTL sampling

receiver or as an LVTTL-to-GTL interface.

The GTL2018 LVTTL inputs (only) are tolerant up to 5.5 V, allowing direct access to TTL

or 5 V CMOS inputs.

2. Features

I Operates as an octal GTL−/GTL/GTL+ sampling receiver or as an LVTTL to

GTL−/GTL/GTL+ driver

I 3.0 V to 3.6 V operation with 5 V tolerant LVTTL input

I GTL input and output 3.6 V tolerant

I V_refadjustable from 0.5 V to 0.5V_CC

I Partial power-down permitted

I Latch-up protection exceeds 500 mA per JESD78

I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-CC101

I Package offered: TSSOP24

3. Quick reference data

Table 1.

Symbol

C_i

Quick reference data

Parameter

Conditions

Min

Typ

Max

Unit

input capacitance

control inputs;

2.5

V_I= 3.0 V or 0 V

C_io

input/output capacitance

A port; V_O= 3.0 V or 0 V

B port; V_O= V_TTor 0 V

4.6

3.4

4.3

GTL; V_ref= 0.8 V; V_TT= 1.2 V

t_PLH

t_PHL

t_PLH

t_PHL

LOW-to-HIGH propagation delay

An to Bn; see Figure 3

Bn to An; see Figure 4

2.8

3.4

5.2

4.9

HIGH-to-LOW propagation delay

LOW-to-HIGH propagation delay

HIGH-to-LOW propagation delay

12 3 4 5 6 7...14

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