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GTL2014PW

更新时间： 2024-11-25 22:48:43

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
15页	78K
描述
4-bit LVTTL to GTL transceiver

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GTL2014PW 数据手册

GTL2014

4-bit LVTTL to GTL transceiver

Rev. 01 — 19 May 2005

Product data sheet

1. General description

The GTL2014 is a 4-bit translating transceiver designed for 3.3 V LVTTL system interface

with a GTL−/GTL/GTL+ bus.

The direction pin allows the part to function as either a GTL to LVTTL sampling receiver or

as a LVTTL to GTL interface.

The GTL2014 LVTTL inputs (only) are tolerant up to 5.5 V allowing direct access to TTL or

5 V CMOS inputs. The LVTTL outputs are not 5.5 V tolerant.

The GTL2014 GTL inputs and outputs operate up to 3.6 V, allowing the device to be used

in higher voltage open-drain output applications.

2. Features

■ Operates as a 4-bit GTL−/GTL/GTL+ sampling receiver or as a LVTTL to

GTL−/GTL/GTL+ driver

■ 3.0 V to 3.6 V operation with 5 V tolerant LVTTL input

■ GTL input and output 3.6 V tolerant

■ V_refadjustable from 0.5 V to V_CC/2

■ Partial power-down permitted

■ ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-CC101

■ Latch-up protection exceeds 500 mA per JESD78

■ Package offered: TSSOP14

3. Quick reference data

Table 1:

Quick reference data

T_amb= 25 °C

Symbol

t_PLH

Parameter

Conditions

Min

Typ

2.8

3.4

5.2

4.9

Max

Unit

propagation delay; An-to-Bn

C_L= 50 pF; V_CC= 3.3 V

t_PHL

t_PLH

propagation delay; Bn-to-An

C_L= 50 pF; V_CC= 3.3 V

V_I= 0 V or V_CC

t_PHL

C_i

input capacitance on pin DIR;

A-to-B or B-to-A

2.5

C_io

input/output capacitance; A-to-B

input/output capacitance; B-to-A

outputs disabled;

V_Iand V_O= 0 V or 3.0 V

4.6

3.4

6.0

4.3

12 3 4 5 6 7...15

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