Datasheet > GTL2009PW

GTL2009PW

更新时间： 2024-11-26 10:37:35

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
17页	88K
描述
3-bit GTL Front-Side Bus frequency comparator

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GTL2009PW 数据手册

GTL2009

3-bit GTL Front-Side Bus frequency comparator

Rev. 01 — 22 September 2005

Product data sheet

1. General description

The GTL2009 is designed for the Nocona and Dempsey/Blackford dual Intel Xeon

processor platforms to compare the Front-Side Bus (FSB) frequency settings and set the

common FSB frequency at the lowest setting if both processor slots are occupied or the

FSB setting of the occupied processor slot if only one processor is being used. A default

FSB frequency of 100 MHz is initially set upon power-up when V_DDis greater than 1.5 V.

Magnitude comparisons and frequency multiplexing to compute the common FSB

frequency occurs when the two 3-bit FSB GTL inputs from the chip sets are valid. The

common FSB frequency GTL outputs switch from the default frequency to the computed

frequency when the GTL reference voltage input (VREF) crosses a static 0.6 V internally

generated input comparator reference voltage. The GTL2009 then continually monitors

the FSB frequency and slot occupied inputs for any further changes.

The Nocona and Dempsey/Blackford Xeon processors specify a V_TTof 1.2 V and 1.1 V,

as well as a nominal V_refof 0.76 V and 0.73 V respectively. To allow for future voltage level

changes that may extend V_refto 0.63 of V_TT(minimum of 0.693 V with V_TTof 1.1 V) the

GTL2009 allows a minimum V_refof 0.66 V. Characterization results show that there is little

DC or AC performance variation between these levels.

The GTL2009 is a companion chip to the GTL2006 platform health management

GTL-to-LVTTL translator and the newer GTL2007 that adds an enable function that

disables the error output to the monitoring agent for platforms that monitor the individual

error conditions from each processor.

2. Features

■ Compares FSB frequency inputs to set the lowest frequency as the common bus

frequency.

■ Operates at a range of GTL signal levels

■ 3.0 V to 3.6 V operation

■ LVTTL I/O are not 5 V tolerant

■ Companion chip to GTL2006 and GTL2007

■ ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115 and 1000 V CDM per JESD22-C101

■ Latch-up testing is done to JEDEC Standard JESD78, which exceeds 500 mA

■ Available in TSSOP16 package

12 3 4 5 6 7...17

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