Datasheet > GS88036BT-300

GS88036BT-300

更新时间： 2024-09-20 04:56:27

品牌	Logo	应用领域
GSI		存储静态存储器
页数	文件大小	规格书
24页	605K
描述
512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs

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数据手册

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GS88036BT-300 数据手册

GS88018/32/36BT-333/300/250/200/150

333 MHz–150 MHz

100-Pin TQFP

Commercial Temp

Industrial Temp

512K x 18, 256K x 32, 256K x 36

9Mb Sync Burst SRAMs

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Features

• FT pin for user-configurable flow through or pipeline

operation

• Single Cycle Deselect (SCD) operation

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

SCD Pipelined Reads

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

• Pb-Free 100-lead TQFP package available

The GS88018/32/36BT is a SCD (Single Cycle Deselect)

pipelined synchronous SRAM. DCD (Dual Cycle Deselect)

versions are also available. SCD SRAMs pipeline deselect

commands one stage less than read commands. SCD RAMs

begin turning off their outputs immediately after the deselect

command has been captured in the input registers.

Functional Description

Applications

The GS88018/32/36BT is a 9,437,184-bit (8,388,608-bit for

x32 version) high performance synchronous SRAM with a

2-bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Controls

Sleep Mode

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS88018/32/36BT operates on a 2.5 V or 3.3 V power

supply. All input are 3.3 V and 2.5 V compatible. Separate

output power (V

) pins are used to decouple output noise

DDQ

from the internal circuits and are 3.3 V and 2.5 V compatible.

Parameter Synopsis

-333

-300

-250

-200

-150

Unit

t_KQ

2.5

3.0

2.5

3.3

2.5

4.0

3.0

5.0

3.8

6.7

tCycle

Pipeline

3-1-1-1

Curr (x18)

Curr (x32/x36)

250

290

230

265

200

230

170

195

140

160

t_KQ

4.5

5.0

5.5

6.5

7.5

tCycle

Flow Through

2-1-1-1

Curr (x18)

Curr (x32/x36)

200

230

185

210

160

185

140

160

128

145

Rev: 1.04 2/2005

1/24

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...24

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与GS88036BT-300相关器件

型号	品牌	获取价格	描述	数据表
GS88036BT-300I	GSI	获取价格	512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88036BT-300IT	ROCHESTER	获取价格	Cache SRAM, 256KX36, 5ns, CMOS, PQFP100, TQFP-100
GS88036BT-333	GSI	获取价格	512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88036BT-333I	GSI	获取价格	512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88036BT-333IT	ROCHESTER	获取价格	Cache SRAM, 256KX36, 4.5ns, CMOS, PQFP100, TQFP-100
GS88036CGT-150	GSI	获取价格	512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88036CGT-150I	GSI	获取价格	Cache SRAM, 256KX36, 7.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS88036CGT-150IT	GSI	获取价格	Cache SRAM, 256KX36, 7.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS88036CGT-150IV	GSI	获取价格	100 TQFP
GS88036CGT-150T	GSI	获取价格	Cache SRAM, 256KX36, 7.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100

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