Datasheet > GS88036CGT-200I

GS88036CGT-200I

更新时间： 2024-09-21 13:48:11

品牌	Logo	应用领域
GSI		/
页数	文件大小	规格书
23页	353K
描述
100 TQFP

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数据手册
替代型号

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GS88036CGT-200I 数据手册

GS88018/32/36CT-xxxI

333 MHz–150 MHz

512K x 18, 256K x 32, 256K x 36

9Mb Sync Burst SRAMs

100-Pin TQFP

Industrial Temp

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Features

• FT pin for user-configurable flow through or pipeline

operation

• Single Cycle Deselect (SCD) operation

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

SCD Pipelined Reads

The GS88018/32/36CT is a SCD (Single Cycle Deselect)

pipelined synchronous SRAM. DCD (Dual Cycle Deselect)

versions are also available. SCD SRAMs pipeline deselect

commands one stage less than read commands. SCD RAMs

begin turning off their outputs immediately after the deselect

command has been captured in the input registers.

Functional Description

Applications

The GS88018/32/36CT is a 9,437,184-bit (8,388,608-bit for

x32 version) high performance synchronous SRAM with a

2-bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Controls

Sleep Mode

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS88018/32/36CT operates on a 2.5 V or 3.3 V power

supply. All input are 3.3 V and 2.5 V compatible. Separate

output power (V

) pins are used to decouple output noise

DDQ

from the internal circuits and are 3.3 V and 2.5 V compatible.

Parameter Synopsis

-333I

-300I

-250I

-200I

-150I

Unit

t_KQ

2.5

3.0

2.5

3.3

2.5

4.0

3.0

5.0

3.8

6.7

tCycle

Pipeline

3-1-1-1

Curr (x18)

Curr (x32/x36)

260

300

245

280

215

245

190

215

160

180

t_KQ

4.5

5.0

5.5

6.5

7.5

tCycle

Flow Through

2-1-1-1

Curr (x18)

Curr (x32/x36)

200

225

185

210

180

200

160

180

148

165

Rev: 1.04 6/2012

1/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...23

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GS88036CGT-200I 替代型号

型号	品牌	替代类型	描述	数据表
GS88036CGT-200	GSI	功能相似	512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs

与GS88036CGT-200I相关器件

型号	品牌	获取价格	描述	数据表
GS88036CGT-200IV	GSI	获取价格	Cache SRAM, 256KX36, 6.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS88036CGT-200V	GSI	获取价格	100 TQFP
GS88036CGT-250	GSI	获取价格	512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88036CGT-250I	GSI	获取价格	100 TQFP
GS88036CGT-250IV	GSI	获取价格	100 TQFP
GS88036CGT-250V	GSI	获取价格	100 TQFP
GS88036CGT-250VT	GSI	获取价格	Cache SRAM, 256KX36, 5.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS88036CGT-300	GSI	获取价格	512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88036CGT-300I	GSI	获取价格	Cache SRAM, 256KX36, 5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS88036CGT-300IT	GSI	获取价格	Cache SRAM, 256KX36, 5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100

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