GS8662T18GE-300T

更新时间： 2024-11-06 13:08:03

品牌	Logo	应用领域
GSI		存储内存集成电路静态存储器双倍数据速率
页数	文件大小	规格书
37页	1792K
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数据手册

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GS8662T18GE-300T 数据手册

Preliminary

GS8662T08/09/18/36E-333/300/267*/250/200/167

333 MHz–167 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

72Mb SigmaCIO DDR-II

Burst of 2 SRAM

1.8 V V

1.8 V and 1.5 V I/O

Features

• Simultaneous Read and Write SigmaCIO™ Interface

• Common I/O bus

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write (x36 and x18) and Nybble Write (x8) function

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 9Mb, 18Mb, 36Mb and future

144Mb devices

Bottom View

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

165-Bump, 15 mm x 17 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

SigmaCIO™ Family Overview

clock inputs, not differential inputs. If the C clocks are tied

high, the K clocks are routed internally to fire the output

registers instead.

The GS8662T08/09/18/36E are built in compliance with the

SigmaCIO DDR-II SRAM pinout standard for Common I/O

synchronous SRAMs. They are 75,497,472-bit (72Mb)

SRAMs. The GS8662T08/09/18/36E SigmaCIO SRAMs are

just one element in a family of low power, low voltage HSTL

I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Common I/O x36 and x18 SigmaCIO DDR-II B2 RAMs

always transfer data in two packets. When a new address is

loaded, A0 presets an internal 1 bit address counter. The

counter increments by 1 (toggles) for each beat of a burst of

two data transfer.

Clocking and Addressing Schemes

The GS8662T08/09/18/36E SigmaCIO DDR-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

C clock inputs. C and C are also independent single-ended

Common I/O x8 SigmaCIO DDR-II B2 RAMs always transfer

data in two packets. When a new address is loaded, the LSB

is internally set to 0 for the first read or write transfer, and

incremented by 1 for the next transfer. Because the LSB is

tied off internally, the address field of a x8 SigmaCIO DDR-II

B4 RAM is always one address pin less than the advertised

index depth (e.g., the 4M x 18 has a 2048K addressable index).

Parameter Synopsis

-333

-300

-267*

-250

-200

-167

tKHKH

tKHQV

3.0 ns

3.3 ns

3.75 ns

4.0 ns

5.0 ns

6.0 ns

0.5 ns

0.45 ns 0.45 ns 0.45 ns 0.45 ns 0.45 ns

* The 267 MHz speed bin is only available on the x18 part.

Rev: 1.01 9/2005

1/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...37

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与GS8662T18GE-300T相关器件

型号	品牌	获取价格	描述	数据表
GS8662T18GE-333	GSI	获取价格	72Mb SigmaCIO DDR-II Burst of 2 SRAM
GS8662T18GE-333I	GSI	获取价格	72Mb SigmaCIO DDR-II Burst of 2 SRAM
GS8662T18GE-333IT	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1MM PITCH, ROHS COMPLIANT, FPBGA-165
GS8662T19AE-400	GSI	获取价格	DDR SRAM, 4MX18, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8662T19AE-400I	GSI	获取价格	DDR SRAM, 4MX18, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8662T19AE-400T	GSI	获取价格	DDR SRAM, 4MX18, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8662T19AGE-375IT	GSI	获取价格	DDR SRAM, 4MX18, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS8662T19BD-300	GSI	获取价格	165 BGA
GS8662T19BD-300I	GSI	获取价格	165 BGA
GS8662T19BD-333	GSI	获取价格	165 BGA

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