Datasheet > GS8662T19BGD-375

GS8662T19BGD-375

更新时间： 2024-11-07 09:00:27

品牌	Logo	应用领域
GSI		双倍数据速率静态存储器
页数	文件大小	规格书
32页	1220K
描述
DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

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GS8662T19BGD-375 数据手册

Preliminary

GS8662T07/10/19/37BD-450/400/350/333/300

72Mb SigmaDDR-II+^TM

Burst of 2 SRAM

450 MHz–300 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

1.8 V V

1.8 V or 1.5 V I/O

Features

• 2.0 Clock Latency

• Simultaneous Read and Write SigmaDDR™ Interface

• Common I/O bus

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 2 Read and Write

• On-Die Termination (ODT) on Data (D), Byte Write (BW),

and Clock (K, K) inputs

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid pin (QVLD) Support

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

Bottom View

165-Bump, 13 mm x 15 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

SigmaDDR™ Family Overview

Clocking and Addressing Schemes

The GS8662T07/10/19/37BD are built in compliance with the

SigmaDDR-II+ SRAM pinout standard for Common I/O

synchronous SRAMs. They are 75,497,472-bit (72Mb)

SRAMs. The GS8662T07/10/19/37BD SigmaDDR-II+

SRAMs are just one element in a family of low power, low

voltage HSTL I/O SRAMs designed to operate at the speeds

needed to implement economical high performance

networking systems.

The GS8662T07/10/19/37BD SigmaDDR-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Because Common I/O SigmaDDR-II+ RAMs always transfer

data in two packets, A0 is internally set to 0 for the first read

or write transfer, and automatically incremented by 1 for the

next transfer. Because the LSB is tied off internally, the

address field of a SigmaDDR-II+ B2 RAM is always one

address pin less than the advertised index depth (e.g., the 4M x

18 has a 2M addressable index).

Parameter Synopsis

-450

-400

2.5 ns

0.45 ns

-350

2.86 ns

0.45 ns

-333

-300

tKHKH

tKHQV

2.22 ns

0.45 ns

3.0 ns

0.45 ns

3.3 ns

0.45 ns

Rev: 1.01 11/2010

1/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...32

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与GS8662T19BGD-375相关器件

型号	品牌	获取价格	描述	数据表
GS8662T19BGD-400	GSI	获取价格	165 BGA
GS8662T19BGD-400I	GSI	获取价格	165 BGA
GS8662T19BGD-450	GSI	获取价格	165 BGA
GS8662T19BGD-450I	GSI	获取价格	165 BGA
GS8662T20AE-300	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8662T20AE-300I	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8662T20AE-300IT	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8662T20AE-333	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8662T20AE-333IT	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8662T20AE-375	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165

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