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GS8662T19BD-375 PDF预览

GS8662T19BD-375

更新时间: 2024-09-17 10:21:51
品牌 Logo 应用领域
GSI 双倍数据速率静态存储器内存集成电路
页数 文件大小 规格书
32页 1220K
描述
DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165

GS8662T19BD-375 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:13 X 15 MM, 1 MM PITCH, FPBGA-165
针数:165Reach Compliance Code:compliant
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
风险等级:5.71最长访问时间:0.45 ns
其他特性:PIPELINED ARCHITECTURE, LATE WRITEJESD-30 代码:R-PBGA-B165
JESD-609代码:e0长度:15 mm
内存密度:75497472 bit内存集成电路类型:DDR SRAM
内存宽度:18功能数量:1
端子数量:165字数:4194304 words
字数代码:4000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4MX18封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:1.4 mm最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:13 mm

GS8662T19BD-375 数据手册

 浏览型号GS8662T19BD-375的Datasheet PDF文件第2页浏览型号GS8662T19BD-375的Datasheet PDF文件第3页浏览型号GS8662T19BD-375的Datasheet PDF文件第4页浏览型号GS8662T19BD-375的Datasheet PDF文件第5页浏览型号GS8662T19BD-375的Datasheet PDF文件第6页浏览型号GS8662T19BD-375的Datasheet PDF文件第7页 
Preliminary  
GS8662T07/10/19/37BD-450/400/350/333/300  
72Mb SigmaDDR-II+TM  
Burst of 2 SRAM  
450 MHz–300 MHz  
165-Bump BGA  
Commercial Temp  
Industrial Temp  
1.8 V V  
DD  
1.8 V or 1.5 V I/O  
Features  
• 2.0 Clock Latency  
• Simultaneous Read and Write SigmaDDR™ Interface  
• Common I/O bus  
• JEDEC-standard pinout and package  
• Double Data Rate interface  
• Byte Write controls sampled at data-in time  
• Burst of 2 Read and Write  
• On-Die Termination (ODT) on Data (D), Byte Write (BW),  
and Clock (K, K) inputs  
• 1.8 V +100/–100 mV core power supply  
• 1.5 V or 1.8 V HSTL Interface  
• Pipelined read operation with self-timed Late Write  
• Fully coherent read and write pipelines  
• ZQ pin for programmable output drive strength  
• Data Valid pin (QVLD) Support  
• IEEE 1149.1 JTAG-compliant Boundary Scan  
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package  
• RoHS-compliant 165-bump BGA package available  
Bottom View  
165-Bump, 13 mm x 15 mm BGA  
1 mm Bump Pitch, 11 x 15 Bump Array  
SigmaDDRFamily Overview  
Clocking and Addressing Schemes  
The GS8662T07/10/19/37BD are built in compliance with the  
SigmaDDR-II+ SRAM pinout standard for Common I/O  
synchronous SRAMs. They are 75,497,472-bit (72Mb)  
SRAMs. The GS8662T07/10/19/37BD SigmaDDR-II+  
SRAMs are just one element in a family of low power, low  
voltage HSTL I/O SRAMs designed to operate at the speeds  
needed to implement economical high performance  
networking systems.  
The GS8662T07/10/19/37BD SigmaDDR-II+ SRAMs are  
synchronous devices. They employ two input register clock  
inputs, K and K. K and K are independent single-ended clock  
inputs, not differential inputs to a single differential clock input  
buffer.  
Because Common I/O SigmaDDR-II+ RAMs always transfer  
data in two packets, A0 is internally set to 0 for the first read  
or write transfer, and automatically incremented by 1 for the  
next transfer. Because the LSB is tied off internally, the  
address field of a SigmaDDR-II+ B2 RAM is always one  
address pin less than the advertised index depth (e.g., the 4M x  
18 has a 2M addressable index).  
Parameter Synopsis  
-450  
-400  
2.5 ns  
0.45 ns  
-350  
2.86 ns  
0.45 ns  
-333  
-300  
tKHKH  
tKHQV  
2.22 ns  
0.45 ns  
3.0 ns  
0.45 ns  
3.3 ns  
0.45 ns  
Rev: 1.01 11/2010  
1/32  
© 2010, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

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