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GS8161EV36BD-150IT PDF预览

GS8161EV36BD-150IT

更新时间： 2024-09-13 14:42:23
品牌 Logo 应用领域
GSI 静态存储器内存集成电路
页数 文件大小 规格书
34页 864K
描述
Cache SRAM, 512KX36, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165

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GS8161EV36BD-150IT 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：13 X 15 MM, 1 MM PITCH, FBGA-165针数：165
Reach Compliance Code：not_compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.92
Is Samacsys：N最长访问时间：7.5 ns
其他特性：FLOW-THROUGH OR PIPELINED ARCHITECTUREJESD-30 代码：R-PBGA-B165
JESD-609代码：e0长度：15 mm
内存密度：18874368 bit内存集成电路类型：CACHE SRAM
内存宽度：36功能数量：1
端子数量：165字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：512KX36封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：1.4 mm最大供电电压 (Vsup)：2 V
最小供电电压 (Vsup)：1.6 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：13 mmBase Number Matches：1

GS8161EV36BD-150IT 数据手册

 浏览型号GS8161EV36BD-150IT的Datasheet PDF文件第2页浏览型号GS8161EV36BD-150IT的Datasheet PDF文件第3页浏览型号GS8161EV36BD-150IT的Datasheet PDF文件第4页浏览型号GS8161EV36BD-150IT的Datasheet PDF文件第5页浏览型号GS8161EV36BD-150IT的Datasheet PDF文件第6页浏览型号GS8161EV36BD-150IT的Datasheet PDF文件第7页 
Preliminary  
GS8161EV18B(T/D)/GS8161EV32B(D)/GS8161EV36B(T/D)  
100-Pin TQFP & 165-Bump BGA  
Commercial Temp  
Industrial Temp  
250 MHz–150 MHz  
1M x 18, 512K x 36, 512K x 36  
18Mb Sync Burst SRAMs  
1.8 V V  
DD  
1.8 V I/O  
either linear or interleave order with the Linear Burst Order (LBO)  
input. The Burst function need not be used. New addresses can be  
loaded on every cycle with no degradation of chip performance.  
Features  
• FT pin for user-configurable flow through or pipeline  
operation  
Flow Through/Pipeline Reads  
• Dual Cycle Deselect (DCD) operation  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• 1.8 V +10%/–10% core power supply  
The function of the Data Output register can be controlled by the  
user via the FT mode pin (Pin 14). Holding the FT mode pin low  
places the RAM in Flow Through mode, causing output data to  
bypass the Data Output Register. Holding FT high places the  
RAM in Pipeline mode, activating the rising-edge-triggered Data  
Output Register.  
• 1.8 V I/O supply  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Default to Interleaved Pipeline mode  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
DCD Pipelined Reads  
The GS8161EV18B(T/D)/GS8161EV32B(D)/GS8161EV36B(T/D)  
is a DCD (Dual Cycle Deselect) pipelined synchronous SRAM.  
SCD (Single Cycle Deselect) versions are also available. DCD  
SRAMs pipeline disable commands to the same degree as read  
commands. DCD RAMs hold the deselect command for one full  
cycle and then begin turning off their outputs just after the second  
rising edge of clock.  
• Automatic power-down for portable applications  
• JEDEC-standard 100-lead TQFP package  
• Pb-Free 100-lead TQFP package available  
Functional Description  
Applications  
Byte Write and Global Write  
The GS8161EV18B(T/D)/GS8161EV32B(D)/GS8161EV36B(T/D)  
is a 18,874,368-bit high performance synchronous SRAM with a  
2-bit burst address counter. Although of a type originally  
developed for Level 2 Cache applications supporting high  
performance CPUs, the device now finds application in  
synchronous SRAM applications, ranging from DSP main store to  
networking chip set support.  
Byte write operation is performed by using Byte Write enable  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the Byte Write control  
inputs.  
Sleep Mode  
Low power (Sleep mode) is attained through the assertion (High)  
of the ZZ signal, or by stopping the clock (CK). Memory data is  
retained during Sleep mode.  
Controls  
Addresses, data I/Os, chip enable (E1), address burst control  
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW,  
GW) are synchronous and are controlled by a positive-edge-  
triggered clock input (CK). Output enable (G) and power down  
control (ZZ) are asynchronous inputs. Burst cycles can be initiated  
with either ADSP or ADSC inputs. In Burst mode, subsequent  
burst addresses are generated internally and are controlled by  
ADV. The burst address counter may be configured to count in  
Core and Interface Voltages  
The GS8161EV18B(T/D)/GS8161EV32B(D)/GS8161EV36B(T/D)  
operates on a 1.8 V power supply. All input are 1.8 V compatible.  
Separate output power (VDDQ) pins are used to decouple output  
noise from the internal circuits and are 1..8 V compatible.  
Parameter Synopsis  
-250  
-200  
-150  
Unit  
tKQ  
tCycle  
2.5  
4.0  
3.0  
5.0  
3.8  
6.7  
ns  
ns  
Pipeline  
3-1-1-1  
280  
330  
230  
270  
185  
210  
mA  
mA  
Curr (x18)  
Curr (x32/x36)  
tKQ  
5.5  
5.5  
6.5  
6.5  
7.5  
7.5  
ns  
ns  
tCycle  
Flow Through  
2-1-1-1  
210  
240  
185  
205  
170  
190  
mA  
mA  
Curr (x18)  
Curr (x32/x36)  
Rev: 1.00 9/2004  
1/34  
© 2004, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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与GS8161EV36BD-150IT相关器件

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GS8161EV36BD-150T GSI

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 		Cache SRAM, 512KX36, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161EV36BGD-150I GSI

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 		Cache SRAM, 512KX36, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161EV36BGD-150IT GSI

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 		Cache SRAM, 512KX36, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161EV36BGD-200I GSI

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 		Cache SRAM, 512KX36, 6.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161EV36BGD-200T GSI

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 		Cache SRAM, 512KX36, 6.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161EV36BGD-250IT GSI

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 		Cache SRAM, 512KX36, 5.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161FZ18BD GSI

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 		18Mb Flow Through Synchronous NBT SRAM
GS8161FZ18BD-5.5 GSI

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 		18Mb Flow Through Synchronous NBT SRAM
GS8161FZ18BD-5.5I GSI

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 		18Mb Flow Through Synchronous NBT SRAM
GS8161FZ18BD-5.5IT GSI

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 		ZBT SRAM, 1MX18, 5.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165

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