Datasheet > GS8161EV36BGD-150I

GS8161EV36BGD-150I

更新时间： 2024-11-06 06:20:43

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
34页	864K
描述
Cache SRAM, 512KX36, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165

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Preliminary

GS8161EV18B(T/D)/GS8161EV32B(D)/GS8161EV36B(T/D)

100-Pin TQFP & 165-Bump BGA

Commercial Temp

Industrial Temp

250 MHz–150 MHz

1M x 18, 512K x 36, 512K x 36

18Mb Sync Burst SRAMs

1.8 V V

1.8 V I/O

either linear or interleave order with the Linear Burst Order (LBO)

input. The Burst function need not be used. New addresses can be

loaded on every cycle with no degradation of chip performance.

Features

• FT pin for user-configurable flow through or pipeline

operation

Flow Through/Pipeline Reads

• Dual Cycle Deselect (DCD) operation

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 1.8 V +10%/–10% core power supply

The function of the Data Output register can be controlled by the

user via the FT mode pin (Pin 14). Holding the FT mode pin low

places the RAM in Flow Through mode, causing output data to

bypass the Data Output Register. Holding FT high places the

RAM in Pipeline mode, activating the rising-edge-triggered Data

Output Register.

• 1.8 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

DCD Pipelined Reads

The GS8161EV18B(T/D)/GS8161EV32B(D)/GS8161EV36B(T/D)

is a DCD (Dual Cycle Deselect) pipelined synchronous SRAM.

SCD (Single Cycle Deselect) versions are also available. DCD

SRAMs pipeline disable commands to the same degree as read

commands. DCD RAMs hold the deselect command for one full

cycle and then begin turning off their outputs just after the second

rising edge of clock.

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

• Pb-Free 100-lead TQFP package available

Functional Description

Applications

Byte Write and Global Write

The GS8161EV18B(T/D)/GS8161EV32B(D)/GS8161EV36B(T/D)

is a 18,874,368-bit high performance synchronous SRAM with a

2-bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main store to

networking chip set support.

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write control

inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High)

of the ZZ signal, or by stopping the clock (CK). Memory data is

retained during Sleep mode.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

ADV. The burst address counter may be configured to count in

Core and Interface Voltages

The GS8161EV18B(T/D)/GS8161EV32B(D)/GS8161EV36B(T/D)

operates on a 1.8 V power supply. All input are 1.8 V compatible.

Separate output power (V_DDQ) pins are used to decouple output

noise from the internal circuits and are 1..8 V compatible.

Parameter Synopsis

-250

-200

-150

Unit

t_KQ

tCycle

2.5

4.0

3.0

5.0

3.8

6.7

Pipeline

3-1-1-1

280

330

230

270

185

210

Curr (x18)

Curr (x32/x36)

t_KQ

5.5

6.5

7.5

tCycle

Flow Through

2-1-1-1

210

240

185

205

170

190

Curr (x18)

Curr (x32/x36)

Rev: 1.00 9/2004

1/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...34

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与GS8161EV36BGD-150I相关器件

型号	品牌	获取价格	描述	数据表
GS8161EV36BGD-150IT	GSI	获取价格	Cache SRAM, 512KX36, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161EV36BGD-200I	GSI	获取价格	Cache SRAM, 512KX36, 6.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161EV36BGD-200T	GSI	获取价格	Cache SRAM, 512KX36, 6.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161EV36BGD-250IT	GSI	获取价格	Cache SRAM, 512KX36, 5.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161FZ18BD	GSI	获取价格	18Mb Flow Through Synchronous NBT SRAM
GS8161FZ18BD-5.5	GSI	获取价格	18Mb Flow Through Synchronous NBT SRAM
GS8161FZ18BD-5.5I	GSI	获取价格	18Mb Flow Through Synchronous NBT SRAM
GS8161FZ18BD-5.5IT	GSI	获取价格	ZBT SRAM, 1MX18, 5.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161FZ18BD-5.5T	GSI	获取价格	ZBT SRAM, 1MX18, 5.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161FZ18BD-6.5	GSI	获取价格	18Mb Flow Through Synchronous NBT SRAM

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