Datasheet > 存储 > SRAM> GS8161FZ32BD-5.5

GS8161FZ32BD-5.5

更新时间： 2024-11-05 05:10:43

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
28页	1238K
描述
18Mb Flow Through Synchronous NBT SRAM

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中文翻译

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数据手册

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GS8161FZ32BD-5.5 数据手册

GS8161FZ18/32/36BD

165-Bump BGA

Commercial Temp

Industrial Temp

5.5 ns–7.5 ns

18Mb Flow Through

Synchronous NBT SRAM

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Features

• Flow Through mode

• NBT (No Bus Turn Around) functionality allows zero wait

read-write-read bus utilization

• Fully pin-compatible with flow through NtRAM™, NoBL™

and ZBT™ SRAMs

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 2.5 V or 3.3 V +10%/–10% core power supply

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2M, 4M, and 8M devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ pin for automatic power-down

• JEDEC-standard 165-bump FP-BGA package

• RoHS-compliant 165-bump BGA package available

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable, ZZ and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS8161FZ18/32/36BD is configured to operate in Flow

Through mode.

The GS8161FZ18/32/36BDis implemented with GSI's high

performance CMOS technology and is available in JEDEC-

standard 165-bump FP-BGA package.

Functional Description

The GS8161FZ18/32/36BD is an 18Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other flow through read/single late write SRAMs, allow

utilization of all available bus bandwidth by eliminating the

need to insert deselect cycles when the device is switched from

read to write cycles.

Parameter Synopsis

-5.5

-6.5

-7.5

Unit

t_KQ

tCycle

5.5

6.5

7.5

Flow Through

2-1-1-1

225

255

200

220

185

205

Curr (x18)

Curr (x32/x36)

Rev: 1.00 6/2006

1/28

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...28

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与GS8161FZ32BD-5.5相关器件

型号	品牌	获取价格	描述	数据表
GS8161FZ32BD-5.5I	GSI	获取价格	18Mb Flow Through Synchronous NBT SRAM
GS8161FZ32BD-6.5	GSI	获取价格	18Mb Flow Through Synchronous NBT SRAM
GS8161FZ32BD-6.5I	GSI	获取价格	18Mb Flow Through Synchronous NBT SRAM
GS8161FZ32BD-6.5IT	GSI	获取价格	ZBT SRAM, 512KX32, 6.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161FZ32BD-6.5T	GSI	获取价格	ZBT SRAM, 512KX32, 6.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161FZ32BD-7.5	GSI	获取价格	18Mb Flow Through Synchronous NBT SRAM
GS8161FZ32BD-7.5I	GSI	获取价格	18Mb Flow Through Synchronous NBT SRAM
GS8161FZ32BGD-5.5	GSI	获取价格	18Mb Flow Through Synchronous NBT SRAM
GS8161FZ32BGD-5.5I	GSI	获取价格	18Mb Flow Through Synchronous NBT SRAM
GS8161FZ32BGD-6.5	GSI	获取价格	18Mb Flow Through Synchronous NBT SRAM

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