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GS8161FZ32BD-6.5I PDF预览

GS8161FZ32BD-6.5I

更新时间: 2024-11-06 05:10:43
品牌 Logo 应用领域
GSI 存储内存集成电路静态存储器
页数 文件大小 规格书
28页 1238K
描述
18Mb Flow Through Synchronous NBT SRAM

GS8161FZ32BD-6.5I 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:LBGA,针数:165
Reach Compliance Code:not_compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.92
Is Samacsys:N最长访问时间:6.5 ns
其他特性:FLOW-THROUGH ARCHITECTURE, IT CAN ALSO OPERATE AT 3.3VJESD-30 代码:R-PBGA-B165
JESD-609代码:e0长度:15 mm
内存密度:16777216 bit内存集成电路类型:ZBT SRAM
内存宽度:32功能数量:1
端子数量:165字数:524288 words
字数代码:512000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:512KX32封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:1.4 mm最大供电电压 (Vsup):2.6 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:13 mmBase Number Matches:1

GS8161FZ32BD-6.5I 数据手册

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GS8161FZ18/32/36BD  
165-Bump BGA  
Commercial Temp  
Industrial Temp  
5.5 ns–7.5 ns  
18Mb Flow Through  
Synchronous NBT SRAM  
2.5 V or 3.3 V V  
DD  
2.5 V or 3.3 V I/O  
Features  
• Flow Through mode  
• NBT (No Bus Turn Around) functionality allows zero wait  
read-write-read bus utilization  
• Fully pin-compatible with flow through NtRAM™, NoBL™  
and ZBT™ SRAMs  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• 2.5 V or 3.3 V +10%/–10% core power supply  
• LBO pin for Linear or Interleave Burst mode  
• Pin-compatible with 2M, 4M, and 8M devices  
• Byte write operation (9-bit Bytes)  
• 3 chip enable signals for easy depth expansion  
• ZZ pin for automatic power-down  
• JEDEC-standard 165-bump FP-BGA package  
• RoHS-compliant 165-bump BGA package available  
Because it is a synchronous device, address, data inputs, and  
read/ write control inputs are captured on the rising edge of the  
input clock. Burst order control (LBO) must be tied to a power  
rail for proper operation. Asynchronous inputs include the  
Sleep mode enable, ZZ and Output Enable. Output Enable can  
be used to override the synchronous control of the output  
drivers and turn the RAM's output drivers off at any time.  
Write cycles are internally self-timed and initiated by the rising  
edge of the clock input. This feature eliminates complex off-  
chip write pulse generation required by asynchronous SRAMs  
and simplifies input signal timing.  
The GS8161FZ18/32/36BD is configured to operate in Flow  
Through mode.  
The GS8161FZ18/32/36BDis implemented with GSI's high  
performance CMOS technology and is available in JEDEC-  
standard 165-bump FP-BGA package.  
Functional Description  
The GS8161FZ18/32/36BD is an 18Mbit Synchronous Static  
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or  
other flow through read/single late write SRAMs, allow  
utilization of all available bus bandwidth by eliminating the  
need to insert deselect cycles when the device is switched from  
read to write cycles.  
Parameter Synopsis  
-5.5  
-6.5  
-7.5  
Unit  
tKQ  
tCycle  
5.5  
5.5  
6.5  
6.5  
7.5  
7.5  
ns  
ns  
Flow Through  
2-1-1-1  
225  
255  
200  
220  
185  
205  
mA  
mA  
Curr (x18)  
Curr (x32/x36)  
Rev: 1.00 6/2006  
1/28  
© 2006, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

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