FDG6302

更新时间： 2024-09-15 22:31:47

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		/
页数	文件大小	规格书
8页	304K
描述
Dual P-Channel, Digital FET

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FDG6302 数据手册

July 1999

FDG6302P

Dual P-Channel, Digital FET

General Description

Features

-25 V, -0.14 A continuous, -0.4 A peak.

These dual P-Channel logic level enhancement mode

field effect transistors are produced using Fairchild's

proprietary, high cell density, DMOS technology. This

very high density process is especially tailored to

minimize on-state resistance. This device has been

designed especially for low voltage applications as a

replacement for bipolar digital transistors and small

R_DS(ON)= 10 W @ V_GS= -4.5 V,

R_DS(ON)= 13 W @ V_GS= -2.7 V.

Very low level gate drive requirements allowing direct

operation in 3 V circuits (V_GS(th)< 1.5 V).

Gate-Source Zener for ESD ruggedness

(>6kV Human Body Model).

signal MOSFETs.

Compact industry standard SC70-6 surface

mount package.

SuperSOT^TM-8

SO-8

SOT-23

SuperSOT^TM-6

SC70-6

SOT-223

1 or 4 *

6 or 3

2 or 5

3 or 6

5 or 2

4 or 1

SC70-6

*The pinouts are symmetrical; pin 1 and 4 are interchangeable.

Units inside the carrier can be of either orientation and will not affect the functionality of the device.

Absolute Maximum Ratings T_A= 25°C unless otherwise noted

Symbol

V_DSS

V_GSS

I_D

Parameter

FDG6302P

-25

Units

Drain-Source Voltage

Gate-Source Voltage

Drain/Output Current

-8

- Continuous

- Pulsed

-0.14

-0.4

P_D

Maximum Power Dissipation

(Note 1)

0.3

°C

T_J,T_STG

ESD

Operating and Storage Temperature Range

-55 to 150

6.0

Electrostatic Discharge Rating MIL-STD-883D

Human Body Model (100 pF / 1500 W)

THERMAL CHARACTERISTICS

R_qJAThermal Resistance, Junction-to-Ambient (Note 1)

415

°C/W

FDG6302P Rev.F1

12 3 4 5 6 7 8

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