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FDG6304 PDF预览

FDG6304

更新时间: 2024-09-15 22:31:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
8页 228K
描述
Dual P-Channel, Digital FET

FDG6304 数据手册

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July 1999  
FDG6304P  
Dual P-Channel, Digital FET  
General Description  
Features  
-25 V, -0.41 A continuous, -1.5 A peak.  
These dual P-Channel logic level enhancement mode  
field effect transistors are produced using Fairchild's  
proprietary, high cell density, DMOS technology. This  
very high density process is especially tailored to  
minimize on-state resistance. This device has been  
designed especially for low voltage applications as a  
replacement for bipolar digital transistors and small  
RDS(ON) = 1.1 W @ VGS= -4.5 V,  
RDS(ON) = 1.5 W @ VGS= -2.7 V.  
Very low level gate drive requirements allowing direct  
operation in 3 V circuits (VGS(th) < 1.5 V).  
Gate-Source Zener for ESD ruggedness  
(>6kV Human Body Model).  
signal MOSFETs.  
Compact industry standard SC70-6 surface  
mount package.  
SuperSOTTM-8  
SO-8  
SOT-23  
SuperSOTTM-6  
SC70-6  
SOT-223  
S2  
1 or 4 *  
G2  
6 or 3  
D1  
2 or 5  
3 or 6  
5 or 2  
4 or 1  
D2  
G1  
S1  
SC70-6  
*
*The pinouts are symmetrical; pin 1 and 4 are interchangeable.  
Units inside the carrier can be of either orientation and will not affect the functionality of the device.  
Absolute Maximum Ratings TA = 25°C unless otherwise noted  
Symbol  
VDSS  
VGSS  
ID  
Parameter  
FDG6304P  
-25  
Units  
V
Drain-Source Voltage  
Gate-Source Voltage  
Drain/Output Current  
-8  
V
- Continuous  
- Pulsed  
-0.41  
-1.5  
A
PD  
Maximum Power Dissipation  
(Note 1)  
0.3  
W
°C  
kV  
TJ,TSTG  
ESD  
Operating and Storage Temperature Range  
-55 to 150  
6.0  
Electrostatic Discharge Rating MIL-STD-883D  
Human Body Model (100 pF / 1500 W)  
THERMAL CHARACTERISTICS  
RqJA Thermal Resistance, Junction-to-Ambient (Note 1)  
415  
°C/W  
FDG6304P Rev.E1  

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