Datasheet > F59D1G81LB-45TG2M

F59D1G81LB-45TG2M

更新时间： 2022-05-14 22:21:07

品牌	Logo	应用领域
晶豪 - ESMT		/
页数	文件大小	规格书
53页	1978K
描述
1 Gbit (128M x 8/ 64M x 16) 1.8V NAND Flash Memory

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ESMT

F59D1G81LB / F59D1G161LB (2M)

Pin Description

Symbol

Pin Name

Functions

The I/O pins are used to input command, address and data, and to output data

during read operations. The I/O pins float to high-z when the chip is deselected

or when the outputs are disabled.

I/O0~I/O7 (x8)

Data Inputs / Outputs

I/O0~I/O15 (x16)

The CLE input controls the activating path for commands sent to the internal

command registers. Commands are latched into the command register

through the I/O ports on the rising edge of the WE# signal with CLE high.

Command Latch

Enable

CLE

ALE

The ALE input controls the activating path for addresses sent to the internal

Address Latch Enable address registers. Addresses are latched into the address register through the

I/O ports on the rising edge of WE# with ALE high.

The RE# input is the device selection control. When the device is in the Busy

state, RE# high is ignored, and the device does not return to standby mode in

program or erase operation. Regarding CE# control during read operation,

CE#

Chip Enable

refer to ’Page read’ section of Device operation.

When LOCK is HIGH during power-up, the BLOCK LOCK function is enabled.

LOCK

To disable BLOCK LOCK, connect LOCK to VSS during power-up, or leave it

unconnected (internal pull-doyn).

LOCK

The RE# input is the serial data-out control, and when it is active low, it

drives the data onto the I/O bus. Data is valid t_REAafter the falling edge of

RE# which also increments the internal column address counter by one.

RE#

WE#

WP#

Read Enable

Write Enable

Write Protect

The WE# input controls writes to the I/O ports. Commands, address and data

are latched on the rising edge of the WE# pulse.

TheWP# pin provides inadvertent write/erase protection during power

transitions. The internal high voltage generator is reset when the WP# pin is

active low.

The R/B# output indicates the status of the device operation. When low, it

indicates that a program, erase or random read operation is in progress and

returns to high state upon completion. It is an open drain output and does not

float to high-z condition when the chip is deselected or when outputs are

disabled.

R/B#

Ready / Busy Output

V_CC

V_SS

Power

V_CCis the power supply for device.

Ground

No Connection

Lead is not internally connected.

Note: Connect all V_CCand V_SSpins of each device to common power supply outputs. Do not leave V_CCor V_SSdisconnected.

Elite Semiconductor Memory Technology Inc.

Publication Date: Aug. 2018

Revision: 1.0 6/53

1...3 4 567 8 9...53

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