ESMT
(Preliminary)
F59L2G81KA (2N)
Flash
2 Gbit (256M x 8)
3.3V NAND Flash Memory
FEATURES
Voltage Supply
1bit/cell
VCC: 3.3V (2.7 V ~ 3.6V)
Command/Address/Data Multiplexed DQ Port
Hardware Data Protection
Organization
Page Size: (2K + 128) bytes
Data Register: (2K + 128) bytes
Block Size: 64Pages = (128K + 8K) bytes
Number of Block per Die (LUN)= 2048
Program/Erase Lockout During Power Transitions
Reliable CMOS Floating Gate Technology
ECC Requirement: 8bit / 512Byte
Endurance: 50K-P/E Cycle Times
Data Retention: 10year
Automatic Program and Erase
Command Register Operation
Number of partial program cycles in the same page (NOP) : 4
Automatic Page 0 Read at Power-Up Option
Page Program: (2K + 128) bytes
Block Erase: (128K + 8K) bytes
Page Read Operation
Write Cycle Time
Boot from NAND support
Random Read: 25us (Max.)
Read Cycle: 25ns
Automatic Memory Download
Cache Program Operation for High Performance Program
Cache Read Operation
Copy-Back Operation
Two-Plane Operation
EDO mode
Page Program Time: 400us (Typ.)
700us (Max.)
Block Erase Time: 3 ms (Typ.)
10ms (Max.)
Page copy
ORDERING INFORMATION
Product ID
Speed
25 ns
25 ns
Package
48 pin TSOPI
63 ball BGA
67 ball BGA
Comments
Pb-free
F59L2G81KA -25TG2N
F59L2G81KA -25BG2N
Pb-free
F59L2G81KA -25BCG2N 25 ns
Pb-free
GENERAL DESCRIPTION
The device has two 2176-byte static registers which allow program and read data to be transferred between the register
and the memory cell array in 2176-byte increments. The Erase operation is implemented in a single block unit (128Kbytes
+ 8Kbytes).
The device is a memory device which utilizes the I/O pins for both address and data input/output as well as command
inputs. The Erase and Program operations are automatically executed making the device most suitable for applications
such as solid state file storage, voice recording, image file memory for still cameras and other systems which require high
density non-volatile memory data storage.
Elite Semiconductor Memory Technology Inc.
Publication Date: Dec. 2019
Revision: 0.2 1/60