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F59D2G81LA-45BG PDF预览

F59D2G81LA-45BG

更新时间： 2024-02-27 05:43:54
品牌 Logo 应用领域
晶豪 - ESMT /
页数 文件大小 规格书
56页 2100K
描述
2 Gbit (256M x 8 / 128M x 16) 1.8V NAND Flash Memory

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F59D2G81LA-45BG 数据手册

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ESMT  
F59D2G81LA / F59D2G161LA  
Flash  
2 Gbit (256M x 8 / 128M x 16)  
1.8V NAND Flash Memory  
FEATURES  
Voltage Supply: 1.8V (1.7V ~ 1.95V)  
Organization  
Command/Address/Data Multiplexed I/O Port  
Hardware Data Protection  
x8:  
- Program/Erase Lockout During Power Transitions  
- Memory Cell Array: (256M + 8M) x 8bit  
- Data Register: (2K + 64) x 8bit  
x16:  
Reliable CMOS Floating Gate Technology  
- ECC Requirement: x8 – 1bit/512Byte  
x16 - 1bit/256 Word  
- Memory Cell Array: (128M + 4M) x 16bit  
- Data Register: (1K + 32) x 16bit  
- Endurance: 100K Program/Erase cycles  
- Data Retention: 10 years  
Automatic Program and Erase  
x8:  
- Page Program: (2K + 64) byte  
- Block Erase: (128K + 4K) byte  
Command Register Operation  
Automatic Page 0 Read at Power-Up Option  
- Boot from NAND support  
- Automatic Memory Download  
x16:  
NOP: 4 cycles  
- Page Program: (1K + 32) word  
- Block Erase: (64K + 2K) word  
Page Read Operation  
- Page Size: (2K + 64) Byte (x8)  
Page Size: (1K + 32) Word (x16)  
- Random Read: 25us (Max.)  
- Serial Access: 45ns (Min.)  
Cache Program/Read Operation  
Copy-Back Operation  
Two-Plane Operation  
EDO mode  
Bad-Block-Protect  
Memory Cell: 1bit/Memory Cell  
Fast Write Cycle Time  
- Program time: 450us (Typ.)  
- Block Erase time: 3.5ms (Typ.)  
ORDERING INFORMATION  
Product ID  
Speed  
Package  
Comments  
x8:  
F59D2G81LA -45TG  
F59D2G81LA -45BG  
x16:  
45 ns  
45 ns  
48 pin TSOPI  
63 ball BGA  
Pb-free  
Pb-free  
F59D2G161LA -45BG 45 ns  
63 ball BGA  
Pb-free  
GENERAL DESCRIPTION  
The device is a 256Mx8bit with spare 8Mx8bit capacity (or  
128Mx16bit with spare 4Mx16bit capacity). The device is offered  
in 1.8V VCC Power Supply. Its NAND cell provides the most  
cost-effective solution for the solid state mass storage market.  
The memory is divided into blocks that can be erased  
independently so it is possible to preserve valid data while old  
data is erased.  
Word. The I/O pins serve as the ports for address and command  
inputs as well as data input/output. The copy back function  
allows the optimization of defective blocks management: when a  
page program operation fails the data can be directly  
programmed in another page inside the same array section  
without the time consuming serial data insertion phase. The  
cache program feature allows the data insertion in the cache  
register while the data register is copied into the Flash array.  
This pipelined program operation improves the program  
throughput when long files are written inside the memory. A  
cache read feature is also implemented. This feature allows to  
dramatically improving the read throughput when consecutive  
pages have to be streamed out. This device includes extra  
feature: Automatic Read at Power Up.  
The device contains 2048 blocks, composed by 64 pages  
consisting in two NAND structures of 32 series connected Flash  
cells. A program operation allows to write the 1056-Word page in  
typical 350us and an erase operation can be performed in typical  
3.5ms on a 128K-Byte for X8 device block (or 64K-Word for X16  
device block).  
Data in the page mode can be read out at 45ns cycle time per  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jun. 2018  
Revision: 1.0  
1/56  
1234567...56

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