EDJ2104EDBG

更新时间： 2024-11-28 12:24:55

品牌	Logo	应用领域
尔必达 - ELPIDA		驱动
页数	文件大小	规格书
150页	1891K
描述
ZQ calibration for DQ drive and ODT

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中文翻译

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数据手册

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EDJ2104EDBG 数据手册

DATA SHEET

2G bits DDR3L SDRAM

EDJ2104EDBG (512M words × 4 bits)

EDJ2108EDBG (256M words × 8 bits)

Features

Specifications

• Density: 2G bits

• Organization

64M words × 4 bits × 8 banks (EDJ2104EDBG)

32M words × 8 bits × 8 banks (EDJ2108EDBG)

• Package

• Double-data-rate architecture: two data transfers per

clock cycle

• The high-speed data transfer is realized by the 8 bits

prefetch pipelined architecture

• Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

78-ball FBGA

Lead-free (RoHS compliant) and Halogen-free

• Power supply: 1.35V (typ.)

VDD, VDDQ = 1.283V to 1.45V

• DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

Backward compatible for VDD, VDDQ

transitions

= 1.5V ± 0.075V

• Commands entered on each positive CK edge; data

• Data rate

1600Mbps/1333Mbps/1066Mbps (max.)

• 1KB page size

and data mask referenced to both edges of DQS

• Data mask (DM) for write data

• Posted /CAS by programmable additive latency for

Row address: A0 to A14

better command and data bus efficiency

Column address: A0 to A9, A11 (EDJ2104EDBG)

• On-Die Termination (ODT) for better signal quality

Synchronous ODT

A0 to A9 (EDJ2108EDBG)

• Eight internal banks for concurrent operation

• Burst lengths (BL): 8 and 4 with Burst Chop (BC)

• Burst type (BT):

Sequential (8, 4 with BC)

Interleave (8, 4 with BC)

• /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11

• /CAS Write Latency (CWL): 5, 6, 7, 8

Dynamic ODT

Asynchronous ODT

• Multi Purpose Register (MPR) for pre-defined pattern

read out

• ZQ calibration for DQ drive and ODT

• Programmable Partial Array Self-Refresh (PASR)

• /RESET pin for Power-up sequence and reset

• Precharge: auto precharge option for each burst

function

access

• SRT range:

Normal/extended

• Programmable Output driver impedance control

• Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)

• Refresh: auto-refresh, self-refresh

• Refresh cycles

Average refresh period

7.8µs at 0°C ≤ TC ≤ +85°C

3.9µs at +85°C < TC ≤ +95°C

• Operating case temperature range

TC = 0°C to +95°C

Document No. E1797E41 (Ver. 4.1)

Date Published February 2012 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2011-2012

12 3 4 5 6 7...150

中文翻译

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与EDJ2104EDBG相关器件

型号	品牌	获取价格	描述	数据表
EDJ2104EDBG-AE-F	ELPIDA	获取价格	Differential clock inputs
EDJ2104EDBG-DJ-F	ELPIDA	获取价格	ZQ calibration for DQ drive and ODT
EDJ2104EDBG-GN-F	ELPIDA	获取价格	Differential clock inputs
EDJ2108BASE-8C-F	ELPIDA	获取价格	2G bits DDR3 SDRAM
EDJ2108BASE-AE-F	ELPIDA	获取价格	2G bits DDR3 SDRAM
EDJ2108BASE-DJ-F	ELPIDA	获取价格	2G bits DDR3 SDRAM
EDJ2108BASE-GN-F	ELPIDA	获取价格	2G bits DDR3 SDRAM
EDJ2108BCSE-8C-F	ELPIDA	获取价格	DDR DRAM, 256MX8, 20ns, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78
EDJ2108BCSE-AE-F	ELPIDA	获取价格	DDR DRAM, 256MX8, 20ns, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78
EDJ2108BCSE-DJ-F	ELPIDA	获取价格	DDR DRAM, 256MX8, 20ns, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78

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