Datasheet > DS90CR211MDC

DS90CR211MDC

更新时间： 2024-11-06 21:16:51

品牌	Logo	应用领域
美国国家半导体 - NSC		驱动接口集成电路驱动器
页数	文件大小	规格书
19页	323K
描述
IC TRIPLE LINE DRIVER, UUC, DIE, Line Driver or Receiver

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

DS90CR211MDC 技术参数

生命周期：	Obsolete	包装说明：	DIE, DIE OR CHIP
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.72
差分输出：	YES	驱动器位数：	3
输入特性：	STANDARD	接口集成电路类型：	LINE DRIVER
接口标准：	GENERAL PURPOSE	JESD-30 代码：	X-XUUC-N
功能数量：	3	最高工作温度：	70 °C
最低工作温度：	-10 °C	封装主体材料：	UNSPECIFIED
封装代码：	DIE	封装等效代码：	DIE OR CHIP
封装形状：	UNSPECIFIED	封装形式：	UNCASED CHIP
电源：	5 V	认证状态：	Not Qualified
最大接收延迟：		子类别：	Line Driver or Receivers
最大压摆率：	53 mA	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	NO LEAD
端子位置：	UPPER	Base Number Matches：	1

DS90CR211MDC 数据手册

July 1997

DS90CR211/DS90CR212

21-Bit Channel Link

needed. This provides a 80% reduction in required cable

width, providing a system cost savings, reduces connector

physical size, and reduces shielding requirements due to the

cables smaller form factor.

General Description

The DS90CR211 transmitter converts 21 bits of CMOS/TTL

data into three LVDS (Low Voltage Differential Signaling)

data streams. A phase-locked transmit clock is transmitted in

parallel with the data streams over a fourth LVDS link. Every

cycle of the transmit clock 21 bits of input data are sampled

and transmitted. The DS90CR212 receiver converts the

LVDS data streams back into 21 bits of CMOS/TTL data. At

a transmit clock frequency of 40 MHz, 21 bits of TTL data are

transmitted at a rate of 280 Mbps per LVDS data channel.

The 21 CMOS/TTL inputs can support a variety of signal

combinations. For example, 5 4-bit nibbles plus 1 control, or

2 9-bit (byte + parity) and 3 control.

Features

n Narrow bus reduces cable size and cost

Using

Mbit/s(105 Mbyte/s).

a 40 MHz clock, the data throughput is 840

1V Common mode range (ground shifting)

n 290 mV swing LVDS data transmission

n 840 Mbit/s data throughput

n Low swing differential current mode drivers reduce EMI

n Rising edge data strobe

n Power down mode

n Offered in low profile 48-lead TSSOP package

The multiplexing of the data lines provides a substantial

cable reduction. Long distance parallel single-ended buses

typically require a ground wire per active signal (and have

very limited noise rejection capability). Thus, for a 21-bit wide

data bus and one clock, up to 44 conductors are required.

With the Channel Link chipset as few as 9 conductors (3

data pairs, 1 clock pair and a minimum of one ground) are

Block Diagrams

DS90CR211

DS90CR212

DS012637-27

DS012637-1

Order Number DS90CR211MTD

See NS Package Number MTD48

Order Number DS90CR212MTD

See NS Package Number MTD48

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

DS012637

www.national.com

12 3 4 5 6 7...19

中文翻译

下载PDF

与DS90CR211MDC相关器件

型号	品牌	获取价格	描述	数据表
DS90CR211MTD	NSC	获取价格	21-Bit Channel Link
DS90CR211MTDX	TI	获取价格	DS90CR211/DS90CR212 21-Bit Channel Link
DS90CR211MWC	NSC	获取价格	暂无描述
DS90CR211MWC	TI	获取价格	TRIPLE LINE DRIVER, UUC, WAFER
DS90CR212	TI	获取价格	DS90CR211/DS90CR212 21-Bit Channel Link
DS90CR212MTD	NSC	获取价格	21-Bit Channel Link
DS90CR212MTDX	TI	获取价格	QUAD LINE RECEIVER, PDSO48, PLASTIC, TSSOP-48
DS90CR212MWC	NSC	获取价格	TRIPLE LINE RECEIVER, UUC, WAFER
DS90CR213	NSC	获取价格	21-Bit Channel LinkΑ66 MHz
DS90CR213	TI	获取价格	21-Bit Channel Link-66 MHz

与DS90CR211MDC相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

14
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

12
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

36
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

33

产品中心

服务支持

精选活动

关于我们

帮助中心

DS90CR211MDC

DS90CR211MDC 技术参数

DS90CR211MDC 数据手册

与DS90CR211MDC相关器件

与DS90CR211MDC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

DS90CR211MDC

DS90CR211MDC 技术参数

DS90CR211MDC 数据手册

与DS90CR211MDC相关器件

与DS90CR211MDC相关文章

您还可以找

您在本页遇到什么问题？