5秒后页面跳转
DS90CR213 PDF预览

DS90CR213

更新时间: 2024-11-06 04:39:11
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
15页 702K
描述
21-Bit Channel Link-66 MHz

DS90CR213 数据手册

 浏览型号DS90CR213的Datasheet PDF文件第2页浏览型号DS90CR213的Datasheet PDF文件第3页浏览型号DS90CR213的Datasheet PDF文件第4页浏览型号DS90CR213的Datasheet PDF文件第5页浏览型号DS90CR213的Datasheet PDF文件第6页浏览型号DS90CR213的Datasheet PDF文件第7页 
August 2005  
DS90CR213/DS90CR214  
21-Bit Channel Link—66 MHz  
General Description  
The DS90CR213 transmitter converts 21 bits of CMOS/TTL  
data into three LVDS (Low Voltage Differential Signaling)  
data streams. A phase-locked transmit clock is transmitted in  
parallel with the data streams over a fourth LVDS link. Every  
cycle of the transmit clock 21 bits of input data are sampled  
and transmitted. The DS90CR214 receiver converts the  
LVDS data streams back into 21 bits of CMOS/TTL data. At  
a transmit clock frequency of 66 MHz, 21 bits of TTL data are  
transmitted at a rate of 462 Mbps per LVDS data channel.  
Using a 66 MHz clock, the data throughput is 1.386 Gbit/s  
(173 Mbytes/s).  
width, which provides a system cost savings, reduces con-  
nector physical size and cost, and reduces shielding require-  
ments due to the cable’s smaller form factor.  
The 21 CMOS/TTL inputs can support a variety of signal  
combinations. For example, 5 4-bit nibbles (byte + parity) or  
2 9-bit (byte + 3 parity) and 1 control.  
Features  
n 66 MHz Clock Support  
n Up to 173 Mbytes/s bandwidth  
<
n Low power CMOS design ( 610 mW)  
<
n Power-down mode ( 0.5 mW total)  
The multiplexing of the data lines provides a substantial  
cable reduction. Long distance parallel single-ended buses  
typically require a ground wire per active signal (and have  
very limited noise rejection capability). Thus, for a 21-bit wide  
data and one clock, up to 44 conductors are required. With  
the Channel Link chipset as few as 9 conductors (3 data  
pairs, 1 clock pair and a minimum of one ground) are  
needed. This provides an 80% reduction in required cable  
n Up to 1.386 Gbit/s data throughput  
n Narrow bus reduces cable size and cost  
n 290 mV swing LVDS devices for low EMI  
n PLL requires no external components  
n Low profile 48-lead TSSOP package  
n Rising edge data strobe  
n Compatible with TIA/EIA-644 LVDS Standard  
Block Diagrams  
DS90CR213  
DS90CR214  
01288827  
Order Number DS90CR213MTD  
See NS Package Number MTD48  
01288801  
Order Number DS90CR214MTD  
See NS Package Number MTD48  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 2005 National Semiconductor Corporation  
DS012888  
www.national.com  

与DS90CR213相关器件

型号 品牌 获取价格 描述 数据表
DS90CR213_05 TI

获取价格

21-Bit Channel Link-66 MHz
DS90CR213MTD TI

获取价格

21-Bit Channel Link-66 MHz
DS90CR213MTD ROCHESTER

获取价格

TRIPLE LINE DRIVER, PDSO48, PLASTIC, TSSOP-48
DS90CR213MTD NSC

获取价格

21-Bit Channel LinkΑ66 MHz
DS90CR213MTD/NOPB TI

获取价格

TRIPLE LINE DRIVER, PDSO48, PLASTIC, TSSOP-48
DS90CR213MTDX/NOPB ROCHESTER

获取价格

TRIPLE LINE DRIVER, PDSO48, PLASTIC, TSSOP-48
DS90CR214 TI

获取价格

21-Bit Channel Link-66 MHz
DS90CR214MTD TI

获取价格

21-Bit Channel Link-66 MHz
DS90CR214MTD NSC

获取价格

21-Bit Channel LinkΑ66 MHz
DS90CR214MTD/NOPB TI

获取价格

TRIPLE LINE RECEIVER, PDSO48, PLASTIC, TSSOP-48