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DS90CR213MTD/NOPB PDF预览

DS90CR213MTD/NOPB

更新时间: 2024-11-09 21:11:23
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管接口集成电路驱动器
页数 文件大小 规格书
15页 472K
描述
TRIPLE LINE DRIVER, PDSO48, PLASTIC, TSSOP-48

DS90CR213MTD/NOPB 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP48,.3,20针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.49
差分输出:YES驱动器位数:3
输入特性:STANDARD接口集成电路类型:LINE DRIVER
接口标准:EIA-644; TIA-644JESD-30 代码:R-PDSO-G48
JESD-609代码:e3长度:12.5 mm
湿度敏感等级:2功能数量:3
端子数量:48最高工作温度:70 °C
最低工作温度:-10 °C输出特性:TOTEM-POLE
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP48,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified最大接收延迟:
座面最大高度:1.2 mm子类别:Line Driver or Receivers
最大压摆率:84 mA最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:6.1 mmBase Number Matches:1

DS90CR213MTD/NOPB 数据手册

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OBSOLETE  
DS90CR213, DS90CR214  
www.ti.com  
SNLS125C JULY 1997REVISED APRIL 2013  
DS90CR213/DS90CR214 21-Bit Channel Link66 MHz  
Check for Samples: DS90CR213, DS90CR214  
1
FEATURES  
DESCRIPTION  
The DS90CR213 transmitter converts 21 bits of  
23  
66 MHz Clock Support  
CMOS/TTL data into three LVDS (Low Voltage  
Differential Signaling) data streams. A phase-locked  
transmit clock is transmitted in parallel with the data  
streams over a fourth LVDS link. Every cycle of the  
transmit clock 21 bits of input data are sampled and  
transmitted. The DS90CR214 receiver converts the  
LVDS data streams back into 21 bits of CMOS/TTL  
data. At a transmit clock frequency of 66 MHz, 21 bits  
of TTL data are transmitted at a rate of 462 Mbps per  
LVDS data channel. Using a 66 MHz clock, the data  
throughput is 1.386 Gbit/s (173 Mbytes/s).  
Up to 173 Mbytes/s Bandwidth  
Low Power CMOS Design (<610 mW)  
Power-down Mode (<0.5 mW total)  
Up to 1.386 Gbit/s Data Throughput  
Narrow Bus Reduces Cable Size and Cost  
290 mV Swing LVDS Devices for Low EMI  
PLL Requires No External Components  
Low Profile 48-Lead TSSOP Package  
Rising Edge Data Strobe  
The multiplexing of the data lines provides  
a
Compatible with TIA/EIA-644 LVDS Standard  
substantial cable reduction. Long distance parallel  
single-ended buses typically require a ground wire  
per active signal (and have very limited noise  
rejection capability). Thus, for a 21-bit wide data and  
one clock, up to 44 conductors are required. With the  
Channel Link chipset as few as 9 conductors (3 data  
pairs, 1 clock pair and a minimum of one ground) are  
needed. This provides an 80% reduction in required  
cable width, which provides a system cost savings,  
reduces connector physical size and cost, and  
reduces shielding requirements due to the cable's  
smaller form factor.  
The 21 CMOS/TTL inputs can support a variety of  
signal combinations. For example, 5 4-bit nibbles  
(byte + parity) or 2 9-bit (byte + 3 parity) and 1  
control.  
BLOCK DIAGRAM  
Figure 1. DS90CR213  
See Package Number DGG0048A  
Figure 2. DS90CR214  
See NS Package Number DGG0048A  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
TRI-STATE is a registered trademark of Texas Instruments.  
2
3
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 1997–2013, Texas Instruments Incorporated  

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