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DS90CR215MTDX/NOPB PDF预览

DS90CR215MTDX/NOPB

更新时间: 2024-02-14 06:42:29
品牌 Logo 应用领域
美国国家半导体 - NSC 驱动光电二极管接口集成电路驱动器
页数 文件大小 规格书
18页 328K
描述
IC LINE DRIVER, PDSO48, LOW PROFILE, PLASTIC, TSSOP-48, Line Driver or Receiver

DS90CR215MTDX/NOPB 技术参数

是否Rohs认证:符合生命周期:Transferred
包装说明:TSSOP, TSSOP48,.3,20Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.14Is Samacsys:N
差分输出:YES驱动器位数:3
输入特性:STANDARD接口集成电路类型:LINE DRIVER
接口标准:EIA-644JESD-30 代码:R-PDSO-G48
JESD-609代码:e3长度:12.5 mm
湿度敏感等级:2功能数量:1
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP48,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified最大接收延迟:
座面最大高度:1.1 mm子类别:Line Driver or Receivers
最大压摆率:55 mA最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:6.1 mmBase Number Matches:1

DS90CR215MTDX/NOPB 数据手册

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June 5, 2009  
DS90CR215/DS90CR216  
+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link -  
66 MHz  
The 21 CMOS/TTL inputs can support a variety of signal  
combinations. For example, five 4-bit nibbles plus 1 control,  
General Description  
The DS90CR215 transmitter converts 21 bits of CMOS/TTL  
data into three LVDS (Low Voltage Differential Signaling) data  
streams. A phase-locked transmit clock is transmitted in par-  
allel with the data streams over a fourth LVDS link. Every  
cycle of the transmit clock 21 bits of input data are sampled  
and transmitted. The DS90CR216 receiver converts the  
LVDS data streams back into 21 bits of CMOS/TTL data. At  
a transmit clock frequency of 66 MHz, 21 bits of TTL data are  
transmitted at a rate of 462 Mbps per LVDS data channel.  
Using a 66 MHz clock, the data throughput is 1.386 Gbit/s  
(173 Mbytes/s).  
or two 9-bit (byte + parity) and 3 control.  
Features  
Single +3.3V supply  
Chipset (Tx + Rx) power consumption <250 mW (typ)  
Power-down mode (<0.5 mW total)  
Up to 173 Megabytes/sec bandwidth  
Up to 1.386 Gbps data throughput  
Narrow bus reduces cable size  
290 mV swing LVDS devices for low EMI  
The multiplexing of the data lines provides a substantial cable  
reduction. Long distance parallel single-ended buses typically  
require a ground wire per active signal (and have very limited  
noise rejection capability). Thus, for a 21-bit wide data and  
one clock, up to 44 conductors are required. With the Channel  
Link chipset as few as 9 conductors (3 data pairs, 1 clock pair  
and a minimum of one ground) are needed. This provides a  
80% reduction in required cable width, which provides a sys-  
tem cost savings, reduces connector physical size and cost,  
and reduces shielding requirements due to the cables' smaller  
form factor.  
+1V common mode range (around +1.2V)  
PLL requires no external components  
Low profile 48-lead TSSOP package  
Rising edge data strobe  
Compatible with TIA/EIA-644 LVDS standard  
ESD Rating > 7 kV  
Operating Temperature: −40°C to +85°C  
Block Diagrams  
DS90CR215  
DS90CR216  
1290901  
1290927  
Order Number DS90CR215MTD  
See NS Package Number MTD48  
Order Number DS90CR216MTD  
See NS Package Number MTD48  
See DS90CR216AMTD with Improved AC Specifications  
Recommended Alternative Device  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 2009 National Semiconductor Corporation  
12909  
www.national.com  

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