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DS90CR218A PDF预览

DS90CR218A

更新时间: 2024-01-19 04:35:38
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
15页 286K
描述
+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 85 MHz

DS90CR218A 数据手册

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November 1999  
DS90CR218A/DS90CR217  
+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel  
Link - 85 MHz  
General Description  
Features  
n 20 to 85 MHz shift clock support  
n 50% duty cycle on receiver output clock  
n Best–in–Class Set & Hold Times on TxINPUTs  
n Low power consumption  
The DS90CR217 transmitter converts 21 bits of CMOS/TTL  
data into three LVDS (Low Voltage Differential Signaling)  
data streams. A phase-locked transmit clock is transmitted in  
parallel with the data streams over a fourth LVDS link. Every  
cycle of the transmit clock 21 bits of input data are sampled  
and transmitted. The DS90CR218A receiver converts the  
three LVDS data streams back into 21 bits of CMOS/TTL  
data. At a transmit clock frequency of 85 MHz, 21 bits of TTL  
data are transmitted at a rate of 595 Mbps per LVDS data  
channel. Using a 85 MHz clock, the data throughput is 1.785  
Gbit/s (223 Mbytes/sec).  
±
n
1V common mode range (around +1.2V)  
n Narrow bus reduces cable size and cost  
n Up to 1.785 Gbps throughput  
n Up to 223 Megabytes/sec bandwidth  
n 345 mV (typ) swing LVDS devices for low EMI  
n PLL requires no external components  
n Rising edge data strobe  
This chipset is an ideal means to solve EMI and cable size  
problems associated with wide, high speed TTL interfaces.  
n Compatible with TIA/EIA-644 LVDS standard  
n Low profile 48-lead TSSOP package  
Block Diagrams  
DS90CR217  
DS90CR218A  
DS101080-1  
DS101080-27  
Order Number DS90CR217MTD  
See NS Package Number MTD48  
Order Number DS90CR218AMTD  
See NS Package Number MTD48  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 1999 National Semiconductor Corporation  
DS101080  
www.national.com  

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