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DS90CR218A PDF预览

DS90CR218A

更新时间: 2023-09-03 20:26:56
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
21页 684K
描述
+3.3V 上升沿数据选通 LVDS 21 位频道链接接收器 - 85MHz

DS90CR218A 数据手册

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DS90CR218A  
www.ti.com  
SNLS054D NOVEMBER 1999REVISED APRIL 2013  
DS90CR218A +3.3V Rising Edge Data Strobe LVDS  
21-Bit Channel Link - 12 MHz to 85 MHz  
Check for Samples: DS90CR218A  
1
FEATURES  
DESCRIPTION  
12 to 85 MHz Shift Clock Support  
The DS90CR218A receiver deserializes three input  
LVDS data streams into 21 bits of CMOS/TTL output  
data. When operating at the maximum input clock  
rate of 85 Mhz, the LVDS data is received at 595  
Mbps per data channel for a total data throughput of  
1.785 Gbit/sec (233 Mbytes/sec).  
50% Duty Cycle on Receiver Output Clock  
Low Power Consumption  
±1V Common-mode Range (Around +1.2V)  
Narrow Bus Reduces Cable Size and Cost  
Up to 1.785 Gbps Throughput  
The narrow bus and LVDS signalling of the  
DS90CR218A is an ideal means to solve EMI and  
cable size problems associated with wide, high-speed  
TTL interfaces.  
Up to 223 Mbytes/sec Bandwidth  
345 mV (typ) Swing LVDS Devices for Low EMI  
PLL Requires No External Components  
Rising Edge Data Strobe  
Compatible with TIA/EIA-644 LVDS Standard  
Low Profile 48-Lead TSSOP Package  
Block Diagram  
Figure 1. DS90CR218A Top View  
See Package Number DGG-48 (TSSOP)  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1999–2013, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

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