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DS90CR218A_06 PDF预览

DS90CR218A_06

更新时间: 2024-02-21 01:12:37
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
11页 615K
描述
+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 12 MHz to 85 MHz

DS90CR218A_06 数据手册

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October 2006  
DS90CR218A  
+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel  
Link - 12 MHz to 85 MHz  
General Description  
Features  
n 12 to 85 MHz shift clock support  
n 50% duty cycle on receiver output clock  
n Low power consumption  
The DS90CR218A receiver deserializes three input LVDS  
data streams into 21 bits of CMOS/TTL output data. When  
operating at the maximum input clock rate of 85 Mhz, the  
LVDS data is received at 595 Mbps per data channel for a  
total data throughput of 1.785 Gbit/sec (233 Mbytes/sec).  
n
1V common-mode range (around +1.2V)  
n Narrow bus reduces cable size and cost  
n Up to 1.785 Gbps throughput  
n Up to 223 Mbytes/sec bandwidth  
n 345 mV (typ) swing LVDS devices for low EMI  
n PLL requires no external components  
n Rising edge data strobe  
The narrow bus and LVDS signalling of the DS90CR218A is  
an ideal means to solve EMI and cable size problems asso-  
ciated with wide, high-speed TTL interfaces.  
n Compatible with TIA/EIA-644 LVDS standard  
n Low profile 48-lead TSSOP package  
Block Diagram  
Connection Diagrams  
DS90CR218A  
10108027  
Order Number DS90CR218AMTD  
See NS Package Number MTD48  
10108022  
DS90CR218A  
© 2006 National Semiconductor Corporation  
DS101080  
www.national.com  

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