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DS90CR214MTDX PDF预览

DS90CR214MTDX

更新时间: 2024-11-25 21:21:07
品牌 Logo 应用领域
德州仪器 - TI 光电二极管接口集成电路
页数 文件大小 规格书
15页 701K
描述
TRIPLE LINE RECEIVER, PDSO48, PLASTIC, TSSOP-48

DS90CR214MTDX 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:TSSOP, TSSOP48,.3,20Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.5差分输出:NO
输入特性:DIFFERENTIAL接口集成电路类型:LINE RECEIVER
接口标准:EIA-644; TIA-644JESD-30 代码:R-PDSO-G48
JESD-609代码:e0长度:12.5 mm
湿度敏感等级:2功能数量:3
端子数量:48最高工作温度:70 °C
最低工作温度:-10 °C输出特性:TOTEM-POLE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP48,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):235电源:5 V
认证状态:Not Qualified最大接收延迟:
接收器位数:3座面最大高度:1.2 mm
子类别:Line Driver or Receivers最大压摆率:140 mA
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:6.1 mm
Base Number Matches:1

DS90CR214MTDX 数据手册

 浏览型号DS90CR214MTDX的Datasheet PDF文件第2页浏览型号DS90CR214MTDX的Datasheet PDF文件第3页浏览型号DS90CR214MTDX的Datasheet PDF文件第4页浏览型号DS90CR214MTDX的Datasheet PDF文件第5页浏览型号DS90CR214MTDX的Datasheet PDF文件第6页浏览型号DS90CR214MTDX的Datasheet PDF文件第7页 
August 2005  
DS90CR213/DS90CR214  
21-Bit Channel Link—66 MHz  
General Description  
The DS90CR213 transmitter converts 21 bits of CMOS/TTL  
data into three LVDS (Low Voltage Differential Signaling)  
data streams. A phase-locked transmit clock is transmitted in  
parallel with the data streams over a fourth LVDS link. Every  
cycle of the transmit clock 21 bits of input data are sampled  
and transmitted. The DS90CR214 receiver converts the  
LVDS data streams back into 21 bits of CMOS/TTL data. At  
a transmit clock frequency of 66 MHz, 21 bits of TTL data are  
transmitted at a rate of 462 Mbps per LVDS data channel.  
Using a 66 MHz clock, the data throughput is 1.386 Gbit/s  
(173 Mbytes/s).  
width, which provides a system cost savings, reduces con-  
nector physical size and cost, and reduces shielding require-  
ments due to the cable’s smaller form factor.  
The 21 CMOS/TTL inputs can support a variety of signal  
combinations. For example, 5 4-bit nibbles (byte + parity) or  
2 9-bit (byte + 3 parity) and 1 control.  
Features  
n 66 MHz Clock Support  
n Up to 173 Mbytes/s bandwidth  
<
n Low power CMOS design ( 610 mW)  
<
n Power-down mode ( 0.5 mW total)  
The multiplexing of the data lines provides a substantial  
cable reduction. Long distance parallel single-ended buses  
typically require a ground wire per active signal (and have  
very limited noise rejection capability). Thus, for a 21-bit wide  
data and one clock, up to 44 conductors are required. With  
the Channel Link chipset as few as 9 conductors (3 data  
pairs, 1 clock pair and a minimum of one ground) are  
needed. This provides an 80% reduction in required cable  
n Up to 1.386 Gbit/s data throughput  
n Narrow bus reduces cable size and cost  
n 290 mV swing LVDS devices for low EMI  
n PLL requires no external components  
n Low profile 48-lead TSSOP package  
n Rising edge data strobe  
n Compatible with TIA/EIA-644 LVDS Standard  
Block Diagrams  
DS90CR213  
DS90CR214  
01288827  
Order Number DS90CR213MTD  
See NS Package Number MTD48  
01288801  
Order Number DS90CR214MTD  
See NS Package Number MTD48  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 2005 National Semiconductor Corporation  
DS012888  
www.national.com  

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