Datasheet > 驱动程序和接口 > 线路驱动器或接收器> DS90CR212MTD

DS90CR212MTD

更新时间： 2024-11-24 22:50:51

品牌	Logo	应用领域
美国国家半导体 - NSC		线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
页数	文件大小	规格书
14页	258K
描述
21-Bit Channel Link

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技术参数
数据手册

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DS90CR212MTD 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	TSSOP, TSSOP48,.3,20	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.48	Is Samacsys：	N
输入特性：	DIFFERENTIAL	接口集成电路类型：	LINE RECEIVER
接口标准：	GENERAL PURPOSE	JESD-30 代码：	R-PDSO-G48
JESD-609代码：	e0	长度：	12.5 mm
功能数量：	4	端子数量：	48
最高工作温度：	70 °C	最低工作温度：	-10 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装等效代码：	TSSOP48,.3,20	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V	认证状态：	Not Qualified
最大接收延迟：		接收器位数：	4
座面最大高度：	1.1 mm	子类别：	Line Driver or Receivers
最大压摆率：	80 mA	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	6.1 mm	Base Number Matches：	1

DS90CR212MTD 数据手册

July 1997

DS90CR211/DS90CR212

21-Bit Channel Link

needed. This provides a 80% reduction in required cable

width, providing a system cost savings, reduces connector

physical size, and reduces shielding requirements due to the

cables smaller form factor.

General Description

The DS90CR211 transmitter converts 21 bits of CMOS/TTL

data into three LVDS (Low Voltage Differential Signaling)

data streams. A phase-locked transmit clock is transmitted in

parallel with the data streams over a fourth LVDS link. Every

cycle of the transmit clock 21 bits of input data are sampled

and transmitted. The DS90CR212 receiver converts the

LVDS data streams back into 21 bits of CMOS/TTL data. At

a transmit clock frequency of 40 MHz, 21 bits of TTL data are

transmitted at a rate of 280 Mbps per LVDS data channel.

The 21 CMOS/TTL inputs can support a variety of signal

combinations. For example, 5 4-bit nibbles plus 1 control, or

2 9-bit (byte + parity) and 3 control.

Features

n Narrow bus reduces cable size and cost

Using

Mbit/s(105 Mbyte/s).

a 40 MHz clock, the data throughput is 840

1V Common mode range (ground shifting)

n 290 mV swing LVDS data transmission

n 840 Mbit/s data throughput

n Low swing differential current mode drivers reduce EMI

n Rising edge data strobe

n Power down mode

n Offered in low profile 48-lead TSSOP package

The multiplexing of the data lines provides a substantial

cable reduction. Long distance parallel single-ended buses

typically require a ground wire per active signal (and have

very limited noise rejection capability). Thus, for a 21-bit wide

data bus and one clock, up to 44 conductors are required.

With the Channel Link chipset as few as 9 conductors (3

data pairs, 1 clock pair and a minimum of one ground) are

Block Diagrams

DS90CR211

DS90CR212

DS012637-27

DS012637-1

Order Number DS90CR211MTD

See NS Package Number MTD48

Order Number DS90CR212MTD

See NS Package Number MTD48

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

DS012637

www.national.com

12 3 4 5 6 7...14

中文翻译

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与DS90CR212MTD相关器件

型号	品牌	获取价格	描述	数据表
DS90CR212MTDX	TI	获取价格	QUAD LINE RECEIVER, PDSO48, PLASTIC, TSSOP-48
DS90CR212MWC	NSC	获取价格	TRIPLE LINE RECEIVER, UUC, WAFER
DS90CR213	NSC	获取价格	21-Bit Channel LinkΑ66 MHz
DS90CR213	TI	获取价格	21-Bit Channel Link-66 MHz
DS90CR213_05	TI	获取价格	21-Bit Channel Link-66 MHz
DS90CR213MTD	TI	获取价格	21-Bit Channel Link-66 MHz
DS90CR213MTD	ROCHESTER	获取价格	TRIPLE LINE DRIVER, PDSO48, PLASTIC, TSSOP-48
DS90CR213MTD	NSC	获取价格	21-Bit Channel LinkΑ66 MHz
DS90CR213MTD/NOPB	TI	获取价格	TRIPLE LINE DRIVER, PDSO48, PLASTIC, TSSOP-48
DS90CR213MTDX/NOPB	ROCHESTER	获取价格	TRIPLE LINE DRIVER, PDSO48, PLASTIC, TSSOP-48

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