Datasheet > DS32EL0421_09

DS32EL0421_09

更新时间： 2024-11-02 06:54:39

品牌	Logo	应用领域
美国国家半导体 - NSC		双倍数据速率
页数	文件大小	规格书
28页	1289K
描述
125-312.5 MHz FPGA-Link Serializer with DDR LVDS Parallel Interface

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DS32EL0421_09 数据手册

June 2, 2009

DS32EL0421, DS32ELX0421

125 – 312.5 MHz FPGA-Link Serializer with DDR LVDS

Parallel Interface

General Description

Features

The DS32EL0421/DS32ELX0421 is a 125 MHz to 312.5 MHz

(DDR) serializer for high-speed serial transmission over FR-4

printed circuit board backplanes, balanced cables, and optical

fiber. This easy-to-use chipset integrates advanced signal

and clock conditioning functions, with an FPGA friendly inter-

face.

5-bit DDR LVDS parallel data interface

■

Programmable transmit de-emphasis

Configurable output levels (V_OD

)

Selectable DC-balanced encoder

Selectable data scrambler

Remote Sense for automatic detection and negotiation of

link status

The DS32EL0421/DS32ELX0421 serializes up to 5 parallel

input LVDS channels to create a maximum data payload of

3.125 Gbps. If the integrated DC-balance encoding is en-

abled, the maximum data payload achievable is 2.5 Gbps.

On chip LC VCOs

■

Redundant serial output (ELX device only)

The DS32EL0421/DS32ELX0421 serializers feature remote

sense capability to automatically detect and negotiate link

status with its companion DS32EL0124/DS32ELX0124 de-

serializers without requiring an additional feedback path.

Data valid signaling to assist with synchronization of

multiple receivers

Supports AC- and DC-coupled signaling

Integrated CML and LVDS terminations

Configurable PLL loop bandwidth

Programmable output termination (50Ω or 75Ω).

Built-in test pattern generator

■

The parallel LVDS interface reduces FPGA I/O pins, board

trace count and alleviates EMI issues, when compared to tra-

ditional single-ended wide bus interfaces.

The DS32EL0421/DS32ELX0421 is programmable through

a SMBus interface as well as through control pins.

Loss of lock and error reporting

Configurable via SMBus

Target Applications

48-pin LLP package with exposed DAP

Imaging: Industrial, Medical Security, Printers

■

Displays: LED walls, Commercial

Key Specifications

Video Transport

1.25 to 3.125 Gbps serial data rate

■

Communication Systems

125 to 312.5 MHz DDR parallel clock

Test and Measurement

-40° to +85°C temperature range

Industrial Bus

>8 kV ESD (HBM) protection

Low Intrinsic Jitter — 35ps at 3.125 Gbps

■

Typical Application

30032101

300321

www.national.com

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与DS32EL0421_09相关器件

型号	品牌	获取价格	描述	数据表
DS32EL0421SQ	TI	获取价格	5-bit DDR LVDS Parallel Data Interface
DS32EL0421SQ/NOPB	TI	获取价格	具有 DDR LVDS 并行接口的 125MHz 至 312.5MHz FPGA-Link
DS32EL0421SQE	TI	获取价格	5-bit DDR LVDS Parallel Data Interface
DS32EL0421SQE/NOPB	TI	获取价格	125 MHz - 312.5 MHz FPGA-Link Serializer with DDR LVDS Parallel Interface 48-WQFN -40 to 8
DS32EL0421SQX	TI	获取价格	5-bit DDR LVDS Parallel Data Interface
DS32EL0421SQX/NOPB	TI	获取价格	具有 DDR LVDS 并行接口的 125MHz 至 312.5MHz FPGA-Link
DS32ELX0124	NSC	获取价格	125 MHz . 312.5 MHz Deserializer with DDR LVDS Parallel Interface
DS32ELX0124	TI	获取价格	具有 DDR LVDS 并行接口的 125MHz 至 312.5MHz FPGA-Link
DS32ELX0124SQ	NSC	获取价格	125 MHz- 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface
DS32ELX0124SQ/NOPB	TI	获取价格	125 MHz - 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface 48-WQFN -40 to

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