DS32EL0421, DS32ELX0421
www.ti.com
SNLS282F –MAY 2008–REVISED APRIL 2013
DS32EL0421 , DS32ELX0421 125 - 312.5 MHz FPGA-Link Serializer with DDR LVDS
Parallel Interface
Check for Samples: DS32EL0421, DS32ELX0421
1
FEATURES
DESCRIPTION
The DS32EL0421/DS32ELX0421 is a 125 MHz to
312.5 MHz (DDR) serializer for high-speed serial
transmission over FR-4 printed circuit board
backplanes, balanced cables, and optical fiber. This
easy-to-use chipset integrates advanced signal and
clock conditioning functions, with an FPGA friendly
interface.
2
•
5-bit DDR LVDS Parallel Data Interface
Programmable Transmit De-emphasis
•
•
•
•
•
Configurable Output Levels (VOD
)
Selectable DC-balanced Encoder
Selectable Data Scrambler
Remote Sense for Automatic Detection and
Negotiation of Link Status
The DS32EL0421/DS32ELX0421 serializes up to 5
parallel input LVDS channels to create a maximum
data payload of 3.125 Gbps. If the integrated DC-
balance encoding is enabled, the maximum data
payload achievable is 2.5 Gbps.
•
•
•
On Chip LC VCOs
Redundant Serial Output (ELX device only)
Data Valid Signaling to Assist with
Synchronization of Multiple Receivers
The DS32EL0421/DS32ELX0421 serializers feature
remote sense capability to automatically detect and
•
•
•
•
Supports AC- and DC-coupled Signaling
Integrated CML and LVDS Terminations
Configurable PLL Loop Bandwidth
negotiate
link
status
with
its
companion
DS32EL0124/DS32ELX0124 deserializers without
requiring an additional feedback path.
Programmable Output Termination (50Ω or
75Ω).
The parallel LVDS interface reduces FPGA I/O pins,
board trace count and alleviates EMI issues, when
compared to traditional single-ended wide bus
interfaces.
•
•
•
•
Built-in Test Pattern Generator
Loss of Lock and Error Reporting
Configurable via SMBus
The DS32EL0421/DS32ELX0421 is programmable
through a SMBus interface as well as through control
pins.
48-pin WQFN Package with Exposed DAP
TARGET APPLICATIONS
•
•
•
•
•
•
Imaging: Industrial, Medical Security, Printers
Displays: LED Walls, Commercial
Video Transport
Communication Systems
Test and Measurement
Industrial Bus
KEY SPECIFICATIONS
•
•
•
•
•
1.25 to 3.125 Gbps Serial Data Rate
125 to 312.5 MHz DDR Parallel Clock
-40° to +85°C Temperature Range
>8 kV ESD (HBM) Protection
Low Intrinsic Jitter — 35ps at 3.125 Gbps
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated